Peter Lidn
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
1991–1996
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1996 | VTS | A fault model for switch-level simulation of gate-to-drain shorts. | Peter Dahlgren, Peter Lidn |
| 1995 | ISCAS | Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. | Peter Lidn, Peter Dahlgren |
| 1995 | VTS | Switch-level modeling of transistor-level stuck-at faults. | Peter Lidn, Peter Dahlgren |
| 1994 | DAC | Modeling of Intermediate Node States in switch-Level Networks. | Peter Dahlgren, Peter Lidn |
| 1993 | ICCAD | Efficient modeling of switch-level networks containing undetermined logic node states. | Peter Dahlgren, Peter Lidn |
| 1992 | ITC | Transistor Fault Coverage for Self-Testing CMOS Checkers. | Peter Lidn, Peter Dahlgren, Jan Torin |
| 1991 | ITC | Two Fault Injection Techniques for Test of Fault Handling Mechanisms. | Johan Karlsson, Ulf Gunneflo, Peter Lidn, Jan Torin |