Skip to content

Peter M. Maurer

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

18

Venues

6

Active years

1988–2014

Best venue rank

A*

Where they publish

Papers

18 indexed papers, newest first.

YearVenueTitleAuthors
2014DATEA universal symmetry detection algorithm.Peter M. Maurer
2006DATEUsing conjugate symmetries to enhance gate-level simulations.Peter M. Maurer
2001SIGCSEIdentifying an appropriate view of software components for undergraduate education.Allen S. Parrish, Joe Hollingsworth, Peter M. Maurer, Benjamin Shults, Bruce W. Weide
2000DATELogic Simulation Using Networks of State Machines.Peter M. Maurer
2000ICCADEvent Driven Simulation Without Loops or Conditionals.Peter M. Maurer
2000VLSIDState-Machine Based Logic Simulation Using Three Logic Values.Peter M. Maurer, William J. Schilp
1999DATESoftware Bit-Slicing: A Technique for Improving Simulation Performance.Peter M. Maurer, William J. Schilp
1999VLSIDEfficient Simulation for Hierarchical and Partitioned Circuits.Peter M. Maurer
1996ICCADUnit delay simulation with the inversion algorithm.William J. Schilp, Peter M. Maurer
1996VLSIDIs Compiled Simulation Really Faster than Interpreted Simulation?Peter M. Maurer
1994ICCADThe Inversion Algorithm for digital simulation.Peter M. Maurer
1993ICCADParallel multi-delay simulation.Yun Sik Lee, Peter M. Maurer
1992DACTwo New Techniques for Compiled Multi-Delay Logic Simulation.Yun Sik Lee, Peter M. Maurer
1990DACTechniques for Unit-Delay Compiled Simulation.Peter M. Maurer, Zhicheng Wang
1990DACLECSIM: A Levelized Event Driven Compiled Logic Simulation.Zhicheng Wang, Peter M. Maurer
1990ICCADOptimization of the Parallel Technique for Compiled Unit-Delay Simulation.Peter M. Maurer
1989DACScheduling High-Level Blocks for Functional Simulation.Zhicheng Wang, Peter M. Maurer
1988ICPPMapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor.Peter M. Maurer