Peter Suaris
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
11
Venues
4
Active years
1994–2005
Best venue rank
A*
Where they publish
Papers
11 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ASPDAC | A practical cut-based physical retiming algorithm for field programmable gate arrays. | Peter Suaris, Dongsheng Wang, Nan-Chi Chou |
| 2005 | FPGA | The effect of post-layout pin permutation on timing. | Yuzheng Ding, Peter Suaris, Nan-Chi Chou |
| 2005 | ICCAD | Total power-optimal pipelining and parallel processing under process variations in nanometer technology. | Peter Suaris, Taeho Kgil, Keith A. Bowman, Vivek De, Trevor N. Mudge |
| 2005 | ICCAD | Improving the efficiency of static timing analysis with false paths. | Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Chung-Kuan Cheng, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris |
| 2004 | FPGA | Fast adders in modern FPGAs. | Jianhua Liu, Michael Chang, Chung-Kuan Cheng, John F. MacDonald, Nan-Chi Chou, Peter Suaris |
| 2004 | FPGA | Incremental physical resynthesis for timing optimization. | Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou |
| 2003 | DAC | An algebraic multigrid solver for analytical placement with layout based clustering. | Hongyu Chen, Chung-Kuan Cheng, Nan-Chi Chou, Andrew B. Kahng, John F. MacDonald, Peter Suaris, Bo Yao, Zhengyong Zhu |
| 2003 | FPGA | A physical retiming algorithm for field programmable gate arrays. | Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou |
| 2000 | DAC | Fast post-placement rewiring using easily detectable functional symmetries. | Chih-Wei Jim Chang, Chung-Kuan Cheng, Peter Suaris, Malgorzata Marek-Sadowska |
| 1997 | DAC | Interface Timing Verification Drives System Design. | Ajay J. Daga, Peter Suaris |
| 1994 | DAC | A Methodology and Algorithms for Post-Placement Delay Optimization. | Lalgudi N. Kannan, Peter Suaris, Hong-Gee Fang |