| 2025 | ITC | Hybrid Static Learning for ATPG. | Jonathon E. Colburn, Peter Wohl, John A. Waicukauski, Yasunari Kanzawa |
| 2018 | ITC | XLBIST: X-Tolerant Logic BIST. | Peter Wohl, John A. Waicukauski, Gregory A. Maston, Jonathon E. Colburn |
| 2017 | DAC | A New Paradigm for Synthesis of Linear Decompressors. | Emil Gizdarski, Peter Wohl, John A. Waicukauski |
| 2014 | ITC | Fault sharing in a copy-on-write based ATPG system. | X. Cai, Peter Wohl, Daniel Martin |
| 2014 | ITC | Achieving extreme scan compression for SoC Designs. | Peter Wohl, John A. Waicukauski, Jonathon E. Colburn, Milind Sonawane |
| 2013 | ITC | A distributed-multicore hybrid ATPG system. | X. Cai, Peter Wohl |
| 2013 | ITC | Two-level compression through selective reseeding. | Peter Wohl, John A. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, Jonathon E. Colburn |
| 2013 | VTS | Improving test generation by use of majority gates. | Peter Wohl, John A. Waicukauski |
| 2012 | ITC | Hybrid selector for high-X scan compression. | Peter Wohl, John A. Waicukauski, Frederic Neuveux, Jonathon E. Colburn |
| 2012 | VTS | Enhancing testability by structured partial scan. | Peter Wohl, John A. Waicukauski, Jonathon E. Colburn |
| 2010 | DAC | Fully X-tolerant, very high scan compression. | Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski |
| 2010 | ITC | Highly efficient parallel ATPG based on shared memory. | X. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath |
| 2010 | ITC | Increasing PRPG-based compression by delayed justification. | Peter Wohl, John A. Waicukauski, T. Finklea |
| 2008 | ITC | Increasing Scan Compression by Using X-chains. | Peter Wohl, John A. Waicukauski, Frederic Neuveux |
| 2007 | ITC | Fully X-tolerant combinational scan compression. | Peter Wohl, John A. Waicukauski, Sanjay Ramnath |
| 2007 | VTS | Minimizing the Impact of Scan Compression. | Peter Wohl, John A. Waicukauski, Rohit Kapur, Sanjay Ramnath, Emil Gizdarski, Thomas W. Williams, P. Jaini |
| 2007 | VTS | Automated Design and Insertion of Optimal One-Hot Bus Encoders. | Peter Wohl, John A. Waicukauski, Sanjay Patel |
| 2005 | ITC | Efficient compression of deterministic patterns into multiple PRPG seeds. | Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur |
| 2005 | VTS | Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. | Peter Wohl, John A. Waicukauski, Sanjay Patel, Cy Hay, Emil Gizdarski, Ben Mathew |
| 2004 | DAC | Scalable selector architecture for x-tolerant deterministic BIST. | Peter Wohl, John A. Waicukauski, Sanjay Patel |
| 2003 | DAC | Efficient compression and application of deterministic patterns in a logic BIST architecture. | Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin |
| 2003 | ITC | X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. | Peter Wohl, John A. Waicukauski, Sanjay Patel, Minesh B. Amin |
| 2003 | VTS | Analysis and Design of Optimal Combinational Compactors. | Peter Wohl, Leendert M. Huisman |
| 2002 | DAC | Effective diagnostics through interval unloads in a BIST environment. | Peter Wohl, John A. Waicukauski, Sanjay Patel, Gregory A. Maston |
| 2001 | ITC | Design of compactors for signature-analyzers in built-in self-test. | Peter Wohl, John A. Waicukauski, Thomas W. Williams |
| 2000 | ITC | Optimizing the flattened test-generation model for very large designs. | Peter Wohl, John A. Waicukauski |
| 2000 | VTS | P1450.1: STIL for the Simulation Environmen. | Peter Wohl, Nathan Biggs |
| 1999 | ITC | Output in still, input in still. | Peter Wohl |
| 1999 | ITC | Using Verilog simulation libraries for ATPG. | Peter Wohl, John A. Waicukauski |
| 1998 | ITC | Extracting gate-level networks from simulation tables. | Peter Wohl, John A. Waicukauski |
| 1998 | ITC | Defining ATPG rules checking in STIL. | Peter Wohl, John A. Waicukauski |
| 1997 | ITC | A Unified Interface for Scan Test Generation Based on STIL. | Peter Wohl, John A. Waicukauski |
| 1997 | VTS | Using ATPG for clock rules checking in complex scan design. | Peter Wohl, John A. Waicukauski |
| 1996 | ITC | Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. | Peter Wohl, John A. Waicukauski |
| 1996 | VTS | Testing "untestable" faults in three-state circuits. | Peter Wohl, John A. Waicukauski, Matthew Graf |
| 1992 | ICPP | Designing Conceptual Clustering for Parallel Implementation. | Peter Wohl, Thomas W. Christopher |
| 1991 | ICPP | Parallel Conceptual Clustering through Message-Driven Computing. | Peter Wohl, Thomas W. Christopher |
| 1991 | ICTAI | MIMD implementation of neural networks through pipelined, parallel communication trees. | Peter Wohl, Thomas W. Christopher |
| 1990 | ICPP | SIMD Neural Net Mapping on MIMD Architectures. | Peter Wohl, Thomas W. Christopher |