Phillip J. Restle
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
5
Active years
1998–2013
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | VTS | On-chip circuit for measuring multi-GHz clock signal waveforms. | Keith A. Jenkins, Phillip J. Restle, P. Z. Wang, D. Hogenmiller, David W. Boerstler, Thomas J. Bucelot |
| 2011 | ICCAD | Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. | Joseph N. Kozhaya, Phillip J. Restle, Haifeng Qian |
| 2008 | ITC | On-chip Timing Uncertainty Measurements on IBM Microprocessors. | Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem |
| 2007 | ITC | On-chip timing uncertainty measurements on IBM microprocessors. | Robert L. Franch, Phillip J. Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, Gerard Salem |
| 2004 | DAC | Design and implementation of the POWER5 microprocessor. | Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip J. Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson |
| 2003 | ICCD | Design of Resonant Global Clock Distributions. | Steven C. Chan, Kenneth L. Shepard, Phillip J. Restle |
| 2001 | DAC | Technical Visualizations in VLSI Design. | Phillip J. Restle |
| 1999 | DAC | Dealing with Inductance in High-Speed Chip Design. | Phillip J. Restle, Albert E. Ruehli, Steven G. Walker |
| 1998 | ICCAD | Interconnect in high speed designs: problems, methodologies and tools. | Phillip J. Restle, Joel R. Phillips, Ibrahim M. Elfadel |