Pol Marchal
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
2006–2013
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ASPDAC | Design issues in heterogeneous 3D/2.5D integration. | Dragomir Milojevic, Pol Marchal, Erik Jan Marinissen, Geert Van der Plas, Diederik Verkest, Eric Beyne |
| 2011 | DAC | 3D heterogeneous system integration: application driver for 3D technology development. | Eric Beyne, Pol Marchal, Geert Van der Plas |
| 2010 | DAC | 3-D stacked die: now or future? | Samta Bansal, Juan C. Rey, Andrew Yang, Myung-Soo Jang, L. C. Lu, Philippe Magarshack, Pol Marchal, Riko Radojcic |
| 2010 | IOLTS | 3D integration: Circuit design, test, and reliability challenges. | Nikolaos Minas, Ingrid De Wolf, Erik Jan Marinissen, Michele Stucchi, Herman Oprins, Abdelkarim Mercha, Geert Van der Plas, Dimitrios Velenis, Pol Marchal |
| 2010 | ISCAS | 3D NoCs - Unifying inter & intra chip communication. | Igor Loi, Pol Marchal, Antonio Pullini, Luca Benini |
| 2009 | DATE | A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. | Anselme Vignon, Stefan Cosemans, Wim Dehaene, Pol Marchal, Marco Facchini |
| 2006 | ASPDAC | Physical design implementation of segmented buses to reduce communication energy. | Jin Guo, Antonis Papanikolaou, Pol Marchal, Francky Catthoor |