Prasanjeet Das
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2013–2013
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ICCD | Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. | Prasanjeet Das, Sandeep K. Gupta |
| 2013 | VTS | Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning. | Prasanjeet Das, Sandeep K. Gupta |