| 2014 | EuroSys | Aerie: flexible file-system interfaces to storage-class memory. | Haris Volos, Sanketh Nalli, Sankaralingam Panneerselvam, Venkatanathan Varadarajan, Prashant Saxena, Michael M. Swift |
| 2005 | ASPDAC | A perturbation-aware noise convergence methodology for high frequency microprocessors. | Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda |
| 2005 | DAC | Net weighting to reduce repeater counts during placement. | Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar |
| 2005 | ISCAS | A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. | Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani |
| 2004 | ASPDAC | Realizable parasitic reduction for distributed interconnects using matrix pencil technique. | Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang |
| 2004 | DAC | Modeling repeaters explicitly within analytical placement. | Prashant Saxena, Bill Halpin |
| 2002 | ICCD | A System-Level Solution to Domino Synthesis with 2 GHz Application. | B. Chappell, Xinning Wang, Priyadarsan Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain |
| 2001 | DAC | Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. | Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang |
| 1999 | DAC | Crosstalk Minimization Using Wire Perturbations. | Prashant Saxena, C. L. Liu |
| 1999 | VLSID | The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. | Prashant Saxena, Peichen Pan, C. L. Liu |
| 1998 | ICCAD | A performance-driven layer assignment algorithm for multiple interconnect trees. | Prashant Saxena, C. L. Liu |
| 1996 | EuroPar | A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. | Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu |