Rajasekhar Nagulapalli
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2010–2025
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | A 2.9mW Inverter-based Quadrature Phase Clock Generator with ± 0.29° Phase Error. | Mayank Kumar Singh, M. Bhuvanesh, Rajasekhar Nagulapalli, Devarshi Mrinal Das, Mahendra Sakare |
| 2024 | ISCAS | A Wide Range Constant Transconductance Circuit Based on Negative Feedback for Analog Circuits. | Rakesh Kumar Palani, Srishti Agrawal, Ayan Alam Khan, Aadarsh V, Rajasekhar Nagulapalli |
| 2022 | ISCAS | A Novel Sub-1V Bandgap Reference with 17.1 ppm/ | Rajasekhar Nagulapalli, Khaled Hayatleh, Nabil Yassine, S. Barker |
| 2021 | ISCAS | A 15uW, 12 ppm/ | Rajasekhar Nagulapalli, Rakesh Kumar Palani, Sweta Agarwal, Shouri Chatterjee, K. Hayatleh, S. Barker |
| 2010 | VLSID | High Speed Clock and Data Recovery Circuit with Novel Jitter Reduction Technique. | Kunal Desai, Rajasekhar Nagulapalli, Vijay Krishna, Rajkumar Palwai, Pravin Kumar Venkatesan, Vijay Khawshe |