Rajat Chauhan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
1
Active years
2008–2021
Best venue rank
National
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | VLSID | 150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. | Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan |
| 2018 | VLSID | A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. | R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale |
| 2018 | VLSID | Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability Analysis. | Sowmya Sankaranarayanan, Kulkarni Chaitali Vinod, Aswanth Sreekumar, Tonse Laxminidhi, Vipul Singhal, Rajat Chauhan |
| 2013 | VLSID | Input Referred Offset Reduction in Very High Speed Differential Receivers. | Rajat Chauhan, Manigandan Selvam |
| 2008 | VLSID | A Robust Level-Shifter Design for Adaptive Voltage Scaling. | Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree |