A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems.
R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale
Browse the full VLSID paper archive.
R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale
Browse the full VLSID paper archive.