| 2024 | ISCAS | Live Demonstration: Real-time audio and visual inference on the RAMAN TinyML accelerator. | Adithya Krishna, Ashwin Rajesh, Hitesh Pavan Oleti, Anand Chauhan, Shankaranarayanan H, Andr van Schaik, Mahesh Mehendale, Chetan Singh Thakur |
| 2021 | VLSID | 150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. | Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan |
| 2020 | ECCV | DBQ: A Differentiable Branch Quantizer for Lightweight Deep Neural Networks. | Hassan Dbouk, Hetul Sanghvi, Mahesh Mehendale, Naresh R. Shanbhag |
| 2018 | VLSID | A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. | R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale |
| 2014 | ICASSP | A monolithic programmable Ultra-HD video codec engine. | Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Nainala Vyagrheswarudu, Vijayavardhan Baireddy, Pavan Shastry |
| 2014 | ISCAS | A 28nm programmable and low power ultra-HD video codec engine. | Hetul Sanghvi, Mihir N. Mody, Niraj Nandan, Mahesh Mehendale, Subrangshu Das, Dipan Kumar Mandal, Pavan Shastry |
| 2014 | MICRO | Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. | Nagendra Dwarakanath Gulur, Mahesh Mehendale, R. Manikantan, R. Govindarajan |
| 2014 | SIGMETRICS | ANATOMY: an analytical model of memory system performance. | Nagendra Gulur, Mahesh Mehendale, Raman Manikantan, Ramaswamy Govindarajan |
| 2012 | ICS | Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. | Nagendra Dwarakanath Gulur, R. Manikantan, Mahesh Mehendale, R. Govindarajan |
| 2006 | VLSID | SoC - The Road Ahead. | Mahesh Mehendale |
| 2004 | VLSID | Challenges in the Design of Embedded Real-time DSP SoCs. | Mahesh Mehendale |
| 2003 | DAC | Emerging markets: design goes global. | Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei |
| 2003 | ISLPED | Multivoltage scheduling with voltage-partitioned variable storage. | Amitabh Menon, S. K. Nandy, Mahesh Mehendale |
| 2001 | ICCAD | Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-Configurable Encoding. | Subash Chandar G., Mahesh Mehendale, R. Govindarajan |
| 2001 | VLSID | High Level Synthesis Of Multi-Precision Data Flow Graphs. | Vikas Agrawal, Anand Pande, Mahesh Mehendale |
| 2001 | VLSID | Performance Considerations in Embedded DSP based System-On-a-Chip Designs. | Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair |
| 2001 | VLSID | Functional Verification of Programmable DSP Cores. | Mahesh Mehendale, Santhosh Kumar Amanna |
| 2000 | VLSID | Low Power Realization of Residue Number System Based FIR Filters. | M. N. Mahesh, Mahesh Mehendale |
| 2000 | VLSID | Power Reduction Techniques for Portable DSP Applications. | Mahesh Mehendale, Sunil D. Sherlekar |
| 1999 | ISCAS | Improving performance of high precision signal processing algorithms on programmable DSPs. | M. N. Mahesh, Mahesh Mehendale |
| 1999 | VLSID | Improving Area Efficiency of Residue Number System based Implementation of DSP Algorithms. | M. N. Mahesh, Satrajit Gupta, Mahesh Mehendale |
| 1999 | VLSID | Low Power Code Generation of Multiplication-free Linear Transforms. | Mahesh Mehendale, Sunil D. Sherlekar |
| 1998 | ASPDAC | Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. | Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar |
| 1998 | VLSID | Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. | Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh |
| 1998 | VLSID | Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1998 | VLSID | Extensions to Programmable DSP architectures for Reduced Power Dissipation. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1998 | VLSID | mproving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic. | Amit Sinha, Mahesh Mehendale |
| 1997 | VLSID | Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1996 | DAC | Optimized Code Generation of Multiplication-free Linear Transforms. | Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar |
| 1996 | VLSID | Low power realization of FIR filters using multirate architectures. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | ASPDAC | Techniques for low power realization for FIR filters. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | ICCAD | Synthesis of multiplier-less FIR filters with minimum number of additions. | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh |
| 1995 | VLSID | AATMA: an algorithm for technology mapping for antifuse-based FPGAs. | Mahesh Mehendale, M. K. Ram Prasad |
| 1994 | VLSID | Impact of Logic Module Routing Flexibility on the Routability of Antifuse-Based Channelled FPGA Architectures. | Mahesh Mehendale |
| 1994 | VLSID | An Integrated Approach to State Assignment and Sequential Element Selection for FSM Synthesis. | Mahesh Mehendale, Biswadip Mitra |
| 1993 | DAC | MIM: Logic Module Independent Technology Mapping for Design and Evaluation of Antifuse-based FPGAs. | Mahesh Mehendale |
| 1993 | VLSID | Estimating Area Efficiency of Antifuse Based Channelled FPGA Architectures. | Mahesh Mehendale, Kaushik Roy |
| 1992 | VLSID | A System for Behavior Extraction from FPGA Implementations of Synchronous Designs. | Mahesh Mehendale |
| 1991 | ICCAD | SLIM: A System for ASIC Library Management. | Mahesh Mehendale, P. Murugavel, M. Poornima |
| 1989 | ICCAD | FDT-a design tool for switched capacitor filters. | Sattam Dasgupta, Mahesh Mehendale, V. R. Sudershan, Rajeev Jain, Nagaraj Subramanyam, James Hochschild |