Vinod Menezes
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
2
Active years
1996–2021
Best venue rank
National
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | VLSID | 150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. | Vipul Singhal, Rajat Chauhan, Vinod Menezes, R. R. Manikandan, Raveesh Magod, Mahesh Mehendale, Anantha P. Chandrakasan |
| 2018 | VLSID | A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. | R. R. Manikandan, Vipul Kumar Singhal, Rajat Chauhan, Vinod Menezes, Mahesh Mehendale |
| 2013 | VLSID | A 40nm 650Mhz 0.5fJ/Bit/Search TCAM Compiler Using Complementary Bit-cell Architecture. | Rashmi Sachan, Shahid Ali, Chandan Bist, Sunil Misra, Vinod Menezes, Sharad Gupta, Pat Bosshart |
| 2008 | VLSID | A Robust Level-Shifter Design for Adaptive Voltage Scaling. | Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree |
| 2003 | VLSID | Optimization of 1.8V I/O circuits for performance, reliability at the 100nm technology node. | Vinod Menezes, C. B. Keshav, Sushil Gupta, M. Roopashree, S. Krishnan, A. Amerasekera, G. Palau |
| 1996 | HiPC | Spatial frequency based motion estimation for image sequence compression. | Vinod Menezes, Soumitra Kumar Nandy, Biswadip Mitra |