Rajeev Jayaraman
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
5
Active years
1988–2001
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2001 | DAC | Panel: (When) Will FPGAs Kill ASICs? | Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen |
| 2000 | FPL | A Placement Algorithm for FPGA Designs with Multiple I/O Standards. | Jason Helge Anderson, Jim Saunders, Sudip Nag, Chari Madabhushi, Rajeev Jayaraman |
| 1998 | FPGA | A Novel Predictable Segmented FPGA Routing Architecture. | Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance |
| 1991 | ICCAD | A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations. | Rajeev Jayaraman, Rob A. Rutenbar |
| 1988 | ICCD | Error tolerance in parallel simulated annealing techniques. | Rajeev Jayaraman, Frederica Darema |