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Ramn Ruiz Merino

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

14

Venues

6

Active years

1999–2025

Best venue rank

C

Where they publish

Papers

14 indexed papers, newest first.

YearVenueTitleAuthors
2025ISCASInterlaced 6T-10T CMOS in-memory computing circuit for low silicon area pipelined DNNs.Gins Domnech-Asensi, Francisco Javier Andreo-Oliver, Ramn Ruiz Merino, Jos ngel Daz-Madrid
2023ISCASA 12T SRAM in-Memory Computing differential current architecture for CNN implementations.Gins Domnech-Asensi, Ramn Ruiz Merino, Juan Zapata-Prez, Jos ngel Daz-Madrid
2020ISCASMixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations.Jos ngel Daz-Madrid, Gins Domnech-Asensi, Ramn Ruiz Merino, Juan Zapata-Prez, Jos Javier Martnez
2009DATEPower reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing.Jos ngel Daz-Madrid, Harald Neubauer, Hans Hauer, Gins Domnech-Asensi, Ramn Ruiz Merino
2009IWINACPersonal Notes about the Figure and Legate of Professor Mira.Ramn Ruiz Merino
2008ISCASAccurate and reusable macromodeling technique using a fuzzy-logic approach.Gins Domnech-Asensi, Juan Hinojosa, Ramn Ruiz Merino, Jos ngel Daz-Madrid
2007FPLCompression system for the phonocardiographic signal.F. Javier Toledo-Moreo, A. Legaz-Cano, J. Javier Martnez-lvarez, Juan Martnez-Alajarn, Ramn Ruiz Merino
2007IWINACOptimization of the Compression Parameters of a Phonocardiographic Telediagnosis System Using Genetic Algorithms.Juan Martnez-Alajarn, F. Javier Garrigs-Guerrero, Ramn Ruiz Merino
2007IWINACClassification and Diagnosis of Heart Sounds and Murmurs Using Artificial Neural Networks.Juan Martnez-Alajarn, Jos Lpez-Candel, Ramn Ruiz Merino
2006FPLSynthesis on FPAA of a Smart Sthetoscope Analog Subsystem.Gins Domnech-Asensi, Juan Martnez-Alajarn, Ramn Ruiz Merino, Jos-Alejandro Lpez Alcantud
2005IWINACDescription and Simulation of Bio-inspired Systems Using VHDL-AMS.Gins Domnech-Asensi, Jos-Alejandro Lpez Alcantud, Ramn Ruiz Merino
2003IWANNAn Analogue Current-Mode Hardware Design Proposal for Preprocessing Layers in ART-Based Neural Networks.Jos-Alejandro Lpez Alcantud, Jos ngel Daz-Madrid, Hans Hauer, Ramn Ruiz Merino
2003IWANNCurrent Mode CMOS Synthesis of a Motor-Control Neural System.Gins Domnech-Asensi, Ramn Ruiz Merino, Hans Hauer, Jos ngel Daz-Madrid
1999EUSFLATImplementing a fuzzy processor on programmable logic circuits: modularization criteria.Esperanza M. Lpez, Alfonso Aniorte Carbonell, Ramn Ruiz Merino