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Ranjani Narayan

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

19

Venues

8

Active years

1993–2019

Best venue rank

National

Where they publish

Papers

19 indexed papers, newest first.

YearVenueTitleAuthors
2019VLSIDA Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-Design.Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2019VLSIDApplying Modified Householder Transform to Kalman Filter.Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers
2017CASESREDEFINEKavitha T. Madhu, Tarun Singla, S. K. Nandy, Ranjani Narayan, Franois Neumann, Philippe Baufreton
2016VLSIDRHyMe: REDEFINE Hyper Cell Multicore for Accelerating HPC Kernels.Saptarsi Das, Nalesh Sivanandan, Kavitha T. Madhu, Soumitra Kumar Nandy, Ranjani Narayan
2016VLSIDVOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks.Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan
2016VLSIDEfficient Realization of Table Look-Up Based Double Precision Floating Point Arithmetic.Farhad Merchant, Nimash Choudhary, S. K. Nandy, Ranjani Narayan
2016VLSIDAchieving Efficient QR Factorization by Algorithm-Architecture Co-design of Householder Transformation.Farhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2015HPCCCompiling HPC Kernels for the REDEFINE CGRA.Kavitha T. Madhu, Saptarsi Das, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan
2015VLSIDHardware Solution for Real-Time Face Recognition.Gopinath Mahale, Hamsika Mahale, Arnav Goel, S. K. Nandy, S. Bhattacharya, Ranjani Narayan
2015VLSIDMicro-architectural Enhancements in Distributed Memory CGRAs for LU and QR Factorizations.Farhad Merchant, Arka Maity, Mahesh Mahadurkar, Kapil Vatwani, Ishan Munje, Madhava Krishna, Nalesh Sivanandan, Nandhini Gopalan, Soumyendu Raha, S. K. Nandy, Ranjani Narayan
2015VLSIDA Flexible Scalable Hardware Architecture for Radial Basis Function Neural Networks.Mahnaz Mohammadi, Nitin Satpute, Rohit Ronge, Jayesh R. Chandiramani, S. K. Nandy, Aamir Raihan, Tanmay Verma, Ranjani Narayan, Sukumar Bhattacharya
2014VLSIDEfficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR).Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan
2013ISCASHigh throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit.S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan
2011SECRYPTA Method for Flexible Reduction over Binary Fields using a Field Multiplier.Saptarsi Das, Keshavan Varadarajan, Ganesh Garga, Rajdeep Mondal, Ranjani Narayan, S. K. Nandy
2010CASESTowards minimizing execution delays on dynamically reconfigurable processors: a case study on REDEFINE.Ratna Krishnamoorthy, Keshavan Varadarajan, Ganesh Garga, Mythri Alle, S. K. Nandy, Ranjani Narayan, Masahiro Fujita
2009CASESStreaming FFT on REDEFINE-v2: an application-architecture design space exploration.Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan
2007FPLREDEFINE: Architecture of a SoC Fabric for Runtime Composition of Computation Structures.A. N. Satrawala, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan
2006ISPAFramework for Enabling Highly Available Distributed Applications for Utility Computing.J. Lakshmi, S. K. Nandy, Ranjani Narayan, Keshavan Varadarajan
1993ICPPA Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array.S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan