Ravishankar Arunachalam
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
5
Active years
1997–2005
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | VLSID | Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits. | Aniket, Ravishankar Arunachalam |
| 2004 | ICCD | Static Transition Probability Analysis Under Uncertainty. | Siddharth Garg, Siddharth Tata, Ravishankar Arunachalam |
| 2003 | ASPDAC | Predicting short circuit power from timing models. | Emrah Acar, Ravishankar Arunachalam, Sani R. Nassif |
| 2001 | DAC | False Coupling Interactions in Static Timing Analysis. | Ravishankar Arunachalam, Ronald D. Blanton, Lawrence T. Pileggi |
| 2000 | DAC | TACO: timing analysis with coupling. | Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi |
| 1998 | ICCAD | Determination of worst-case aggressor alignment for delay calculation. | Paul D. Gross, Ravishankar Arunachalam, Karthik Rajagopal, Lawrence T. Pileggi |
| 1997 | ICCD | CMOS Gate Delay Models for General RLC Loading. | Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi |