| 2009 | FPL | An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. | Markus Rullmann, Renate Merker, Heiko Hinkelmann, Peter Zipf, Manfred Glesner |
| 2008 | DSD | Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. | Rainer Schaffer, Renate Merker, Frank Hannig, Jrgen Teich |
| 2008 | FPL | Fine grain reconfigurable architectures. | Josef Angermeier, Mateusz Majer, Jrgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hbner, Jrgen Becker, Enno Lbbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker |
| 2006 | EuroPar | Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints. | Sebastian Siegel, Renate Merker |
| 2003 | DSD | Causality Constraints for Processor Architectures with Sub-Word Parallelism. | Rainer Schaffer, Renate Merker, Francky Catthoor |
| 2000 | VLSID | Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel. | Rainer Schaffer, Renate Merker, Francky Catthoor |
| 1999 | EuroPar | Localization of Data Transfer in Processor Arrays. | Dirk Fimmel, Renate Merker |
| 1998 | EuroPar | Design of Processor Arrays for Real-Time Applications. | Dirk Fimmel, Renate Merker |
| 1996 | PDP | Propagation of I/O-Variables in Massively Parallel Processor Arrays. | Dirk Fimmel, Renate Merker |