Renato P. Ribas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
15
Venues
6
Active years
2005–2018
Best venue rank
C
Where they publish
Papers
15 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2018 | ICCAD | Unlocking fine-grain parallelism for AIG rewriting. | Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, Andr Incio Reis |
| 2015 | DSD | Enhanced Spin-Diode Synthesis Using Logic Sharing. | Mayler G. A. Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, Andr Incio Reis |
| 2015 | ICCAD | Threshold Logic Synthesis Based on Cut Pruning. | Augusto Neutzling, Jody Maick Matos, Andr Incio Reis, Renato P. Ribas, Alan Mishchenko |
| 2015 | ICCD | Bottom-up disjoint-support decomposition based on cofactor and boolean difference analysis. | Vinicius Callegaro, Felipe S. Marranghello, Mayler G. A. Martins, Renato P. Ribas, Andr Incio Reis |
| 2015 | ICCD | SOP based logic synthesis for memristive IMPLY stateful logic. | Felipe S. Marranghello, Vinicius Callegaro, Andr Incio Reis, Renato P. Ribas |
| 2015 | ISCAS | Improved logic synthesis for memristive stateful logic using multi-memristor implication. | Felipe S. Marranghello, Vinicius Callegaro, Mayler G. A. Martins, Andr Incio Reis, Renato P. Ribas |
| 2015 | ISCAS | Fast buffer delay estimation considering time-dependent dielectric breakdown. | Felipe S. Marranghello, Andr Incio Reis, Renato P. Ribas |
| 2014 | ISCAS | CMOS inverter analytical delay model considering all operating regions. | Felipe S. Marranghello, Andr Incio Reis, Renato P. Ribas |
| 2014 | ISCAS | A constructive approach for threshold logic circuit synthesis. | Augusto Neutzling, Mayler G. A. Martins, Renato P. Ribas, Andr Incio Reis |
| 2011 | ICCD | Impact and optimization of lithography-aware regular layout in digital circuit design. | Vincius Dal Bem, Paulo F. Butzen, Felipe S. Marranghello, Andr Incio Reis, Renato P. Ribas |
| 2011 | IOLTS | Self-checking test circuits for latches and flip-flops. | Renato P. Ribas, Yuyang Sun, Andr Incio Reis, Andr Ivanov |
| 2010 | DATE | KL-Cuts: A new approach for logic synthesis targeting multiple output blocks. | Osvaldo Martinello, Felipe S. Marques, Renato P. Ribas, Andr Incio Reis |
| 2010 | ICCD | Boolean factoring with multi-objective goals. | Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, Andr Incio Reis |
| 2009 | ISCAS | Efficient Test Circuit to Qualify Logic Cells. | Renato P. Ribas, Simone Bavaresco, Marcelo Lubaszewski, Andr Incio Reis |
| 2005 | ICCD | Exact lower bound for the number of switches in series to implement a combinational logic cell. | Felipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, Andr Incio Reis |