Robert E. Huston
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
1983–1998
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | ITC | A scalable architecture for VLSI test. | Ed Chang, David Cheung, Robert E. Huston, Jim Seaton, Gary Smith |
| 1997 | ITC | Pin Margin Analysis. | Robert E. Huston |
| 1983 | ITC | An Analysis of ATE Testing Costs. | Robert E. Huston |