| 2006 | ISPASS | ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. | Victor Moya Del Barrio, Carlos Gonzlez, Jordi Roca, Agustn Fernndez, Roger Espasa |
| 2005 | MICRO | Shader Performance Analysis on a Modern GPU Architecture. | Victor Moya Del Barrio, Carlos Gonzlez, Jordi Roca, Agustn Fernndez, Roger Espasa |
| 2004 | HPCA | Link-Time Path-Sensitive Memory Redundancy Elimination. | Manel Fernndez, Roger Espasa |
| 2002 | ISCA | Tarantula: A Vector Extension to the Alpha Architecture. | Roger Espasa, Federico Ardanaz, Julio Gago, Roger Gramunt, Isaac Hernandez, Toni Juan, Joel S. Emer, Stephen Felix, P. Geoffrey Lowney, Matthew Mattina, Andr Seznec |
| 2002 | MICRO | Three-dimensional memory vectorization for high bandwidth media memory systems. | Jess Corbal, Roger Espasa, Mateo Valero |
| 2001 | EuroPar | Topic 08+13: Instruction-Level Parallelism and Computer Architecture. | Eduard Ayguad, Fredrik Dahlgren, Christine Eisenbeis, Roger Espasa, Guang R. Gao, Henk L. Muller, Rizos Sakellariou, Andr Seznec |
| 2001 | EuroPar | Load Redundancy Elimination on Executable Code. | Manel Fernndez, Roger Espasa, Saumya K. Debray |
| 2001 | HPCA | DLP + TLP Processors for the Next Generation of Media Workloads. | Jess Corbal, Roger Espasa, Mateo Valero |
| 2001 | SPAA | A cost effective architecture for vectorizable numerical and multimedia applications. | Francisca Quintana, Jess Corbal, Roger Espasa, Mateo Valero |
| 1999 | ICS | Adding a vector unit to a superscalar processor. | Francisca Quintana, Jess Corbal, Roger Espasa, Mateo Valero |
| 1999 | MICRO | Exploiting a New Level of DLP in Multimedia Applications. | Jess Corbal, Roger Espasa, Mateo Valero |
| 1999 | SC | MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. | Jess Corbal, Roger Espasa, Mateo Valero |
| 1998 | ICS | Vector Architectures: Past, Present and Future. | Roger Espasa, Mateo Valero, James E. Smith |
| 1998 | ICS | A Performance Study of Out-of-order Vector Architectures and Short Registers. | Luis Villa, Roger Espasa, Mateo Valero |
| 1998 | MICRO | Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. | Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan |
| 1998 | PDP | A case for merging the ILP and DLP paradigms. | Francisca Quintana, Roger Espasa, Mateo Valero |
| 1998 | PDP | Effective usage of vector registers in decoupled vector architectures. | Luis Villa, Roger Espasa, Mateo Valero |
| 1997 | HiPC | Simultaneous multithreaded vector architecture: merging ILP and DLP for high performance. | Roger Espasa, Mateo Valero |
| 1997 | HPCA | Multithreaded Vector Architectures. | Roger Espasa, Mateo Valero |
| 1997 | ICS | A Victim Cache for Vector Registers. | Roger Espasa, Mateo Valero |
| 1997 | MICRO | Out-of-Order Vector Architectures. | Roger Espasa, Mateo Valero, James E. Smith |
| 1996 | HPCA | Decoupled Vector Architectures. | Roger Espasa, Mateo Valero |
| 1995 | PDP | Quantitative analysis of vector code. | Roger Espasa, Mateo Valero, David A. Padua, Marta Jimnez, Eduard Ayguad |