| 2012 | DDECS | The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector Processor. | Jaroslav Sykora, Lukas Kohout, Roman Bartosinski, Leos Kafka, Martin Danek, Petr Honzk |
| 2012 | DSD | Reducing Instruction Issue Overheads in Application-Specific Vector Processors. | Jaroslav Sykora, Roman Bartosinski, Lukas Kohout, Martin Danek, Petr Honzk |
| 2011 | ICASSP | The LD-RLS algorithmwith directional forgetting implemented on a vector-like hardware accelerator. | Roman Bartosinski |
| 2008 | FPL | Increasing the level of abstraction in FPGA-based designs. | Martin Danek, Jiri Kadlec, Roman Bartosinski, Lukas Kohout |
| 2007 | FPL | Accelerating Microblaze Floating Point Operations. | Jiri Kadlec, Roman Bartosinski, Martin Danek |
| 2006 | ETFA | Processor Expert Enhances Matlab Simulink Facilities for Embedded Software Rapid Development. | Roman Bartosinski, Zdenek Hanzlek, Libor Waszniowski, Petr Struzka |
| 2005 | FPGA | Dynamic reconfiguration in FPGA-based SoC designs (abstract only). | Roman Bartosinski, Martin Danek, Petr Honzk, Rudolf Matousek |