Roshan Weerasekera
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2007–2025
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | DATE | Nanoelectromechanical Binary Comparator for Edge-Computing Applications. | Victor Marot, Manu Bala Krishnan, Mukesh Kumar Kulsreshath, Elliott Worsey, Roshan Weerasekera, Dinesh Pamunuwa |
| 2011 | ICCAD | Modeling the computational efficiency of 2-D and 3-D silicon processors for early-chip planning. | Matthew Grange, Axel Jantsch, Roshan Weerasekera, Dinesh Pamunuwa |
| 2010 | DATE | On signalling over Through-Silicon Via (TSV) interconnects in 3-D Integrated Circuits. | Roshan Weerasekera, Matt Grange, Dinesh Pamunuwa, Hannu Tenhunen |
| 2007 | ICCAD | Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs. | Roshan Weerasekera, Li-Rong Zheng, Dinesh Pamunuwa, Hannu Tenhunen |
| 2007 | VLSID | Delay-Balanced Smart Repeaters for On-Chip Global Signaling. | Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng, Hannu Tenhunen |