| 2026 | ASPDAC | FESTAL: Dataflow Accelerator Synthesis Framework with Graph-Based Fusion for FPGA. | Ruifan Xu, Yuyang Zou, Yun Liang |
| 2026 | ISCA | Graph.hls: A Compiler Framework for Composable Graph Accelerator Design. | Feiyang Wu, Xuxiao Yang, Zhuohang Bian, Jing Wang, Ruifan Xu, Guangyu Sun, Yun Liang, Youwei Zhuo |
| 2026 | ISCA | PipeComm: Maximizing Link Utilization Through Pipeline-Aware Collective Communication Synthesis. | Ruifan Xu, Yuze Luo, Yuhao Meng, Size Zheng, Meng Li, Yun Liang |
| 2025 | ICCAD | Invited Paper: APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization. | Youwei Xiao, Yuyang Zou, Yansong Xu, Yuhao Luo, Yitian Sun, Chenyun Yin, Ruifan Xu, Renze Chen, Yun Liang |
| 2024 | FPGA | Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRs. | Ruifan Xu, Jin Luo, Yun Liang |
| 2024 | MICRO | Hestia: An Efficient Cross-Level Debugger for High-Level Synthesis. | Ruifan Xu, Jin Luo, Yawen Zhang, Yibo Lin, Runsheng Wang, Ru Huang, Yun Liang |
| 2022 | ICCAD | HECTOR: A Multi-Level Intermediate Representation for Hardware Synthesis Methodologies. | Ruifan Xu, Youwei Xiao, Jin Luo, Yun Liang |