Rupesh S. Shelar
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
1999–2020
Best venue rank
A
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2020 | FPGA | An Algorithm for Delay Optimal Logic Replication for FPGAs Accounting for Combinational Loops. | Rupesh S. Shelar |
| 2008 | ICCAD | Delay-optimal simultaneous technology mapping and placement with applications to timing optimization. | Yifang Liu, Rupesh S. Shelar, Jiang Hu |
| 2002 | VLSID | An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. | Rupesh S. Shelar, Sachin S. Sapatnekar |
| 2001 | ICCAD | Recursive Bipartitioning of BDDs for Performance Driven Synthesis of Pass Transistor Logic Circuits. | Rupesh S. Shelar, Sachin S. Sapatnekar |
| 1999 | ICCD | Decomposition of Finite State Machines for Area, Delay Minimization. | Rupesh S. Shelar, Madhav P. Desai, H. Narayanan |