Sadegh Yazdanshenas
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2017–2025
Best venue rank
B
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | FPL | Routing Struggle: A Metric to Quantify Routability. | Sadegh Yazdanshenas, Jeffrey Chromczak |
| 2019 | FPGA | Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs. | Andrew Boutros, Mohamed Eldafrawy, Sadegh Yazdanshenas, Vaughn Betz |
| 2018 | FPL | Embracing Diversity: Enhanced DSP Blocks for Low-Precision Deep Learning on FPGAs. | Andrew Boutros, Sadegh Yazdanshenas, Vaughn Betz |
| 2017 | FPGA | Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration. | Sadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz |
| 2017 | FPL | Quantifying and mitigating the costs of FPGA virtualization. | Sadegh Yazdanshenas, Vaughn Betz |