Sallar Ahmadi-Pour
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
13
Venues
8
Active years
2021–2026
Best venue rank
A*
Where they publish
Papers
13 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DDECS | Security-Aware Benchmarks for Performance Exploration of CHERI-Enabled Architectures. | Spandan Das, Sayak Deb, Khushboo Qayyum, Sallar Ahmadi-Pour, Christoph Lth, Rolf Drechsler |
| 2026 | VLSID | DIVIAC: Library of Input Data Aware Approximate Dividers with Partial Exact Minimization. | Chandan Kumar Jha, Sallar Ahmadi-Pour, Sajjad Parvin, Rolf Drechsler |
| 2025 | DDECS | CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution. | Karl Aaron Rudkowski, Sallar Ahmadi-Pour, Rolf Drechsler |
| 2025 | DDECS | River: Sneak Path Aware READ-based In-Memory Computing for 1T1M Memristive Crossbars. | Till Schnittka, Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler |
| 2025 | ETS | Large Language Models (LLMs) for Verification, Testing, and Design. | Chandan Kumar Jha, Muhammad Hassan, Khushboo Qayyum, Sallar Ahmadi-Pour, Kangwei Xu, Ruidi Qiu, Jason Blocklove, Luca Collini, Andre Nakkab, Ulf Schlichtmann, Grace Li Zhang, Ramesh Karri, Bing Li, Siddharth Garg, Rolf Drechsler |
| 2025 | FDL | System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit. | Deepak Ravibabu, Sallar Ahmadi-Pour, Muhammad Hassan, Abhoy Kole, Chandan Kumar Jha, Rolf Drechsler |
| 2024 | ASPDAC | Security Coverage Metrics for Information Flow at the System Level. | Ece Nur Demirhan Coskun, Sallar Ahmadi-Pour, Muhammad Hassan, Rolf Drechsler |
| 2024 | DAC | Late Breaking Results: LLM-assisted Automated Incremental Proof Generation for Hardware Verification. | Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha, Rolf Drechsler |
| 2024 | DATE | LLM-Guided Formal Verification Coupled with Mutation Testing. | Muhammad Hassan, Sallar Ahmadi-Pour, Khushboo Qayyum, Chandan Kumar Jha, Rolf Drechsler |
| 2024 | VLSID | Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. | Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler |
| 2023 | FDL | Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. | Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
| 2022 | DSD | Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. | Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier |
| 2021 | FDL | RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. | Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |