| 2025 | ICPP | AMPED: Accelerating MTTKRP for Billion-Scale Sparse Tensor Decomposition on Multiple GPUs. | Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna |
| 2024 | ACSSC | Accelerating Sparse MTTKRP for Small Tensor Decomposition on GPU $\mathcal{X}_{(d)}$. | Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna |
| 2023 | FPGA | Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA. | Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna |
| 2023 | FPL | Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration. | Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna |
| 2023 | SBAC-PAD | Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU. | Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna |
| 2022 | DATA | Towards Programmable Memory Controller for Tensor Decomposition. | Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna |
| 2022 | ISPDC | Estimating the Impact of Communication Schemes for Distributed Graph Processing. | Tian Ye, Sanmukh R. Kuppannagari, Csar A. F. De Rose, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna |
| 2021 | HOTI | Programmable FPGA-based Memory Controller. | Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna |
| 2019 | FPGA | Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. | Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual |