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Satoshi Shigematsu

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

9

Venues

7

Active years

1999–2020

Best venue rank

B

Where they publish

Papers

9 indexed papers, newest first.

YearVenueTitleAuthors
2020VTCHierarchical Scheduling with FPGA-based Accelerator for Flexible 5G Mobile Networks.Yuki Arikawa, Takeshi Sakamoto, Satoshi Shigematsu
2019VTC5G R&D Activities for High Capacity Technologies with Ultra High-Density Multi-Band and Multi-Access Layered Cells.Morihiko Minowa, Hiroyuki Seki, Yukihiko Okumura, Satoshi Suyama, Jun Terada, Satoshi Shigematsu, Yasushi Takatori, Hiroaki Asano, Yukio Hirano, Yasushi Yamao, Fumiyuki Adachi, Masataka Nakazawa
2018PIMRCThroughput Enhancement with Hardware Accelerated Resource Scheduler in Low-Latency 5G Systems.Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu
2015APCCHigh-speed sorted-table search scheme for network processing.Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Satoshi Shigematsu
2012FPLWire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano
2002ICPRA Fingerprint Verification Algorithm Using the Differential Matching Rate.Takahiro Hatano, Takuya Adachi, Satoshi Shigematsu, Hiroki Morimura, Shigehiko Onishi, Yukio Okazaki, Hakaru Kyuragi
2002ICPRFingerprint Image Enhancement by Pixel-Parallel Processing.Namiko Ikeda, Mamoru Nakanishi, Koji Fujii, Takahiro Hatano, Satoshi Shigematsu, Takuya Adachi, Yukio Okazaki, Hakaru Kyuragi
1999ASPDACDesign Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs.Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka
1999ISLPEDA shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka