Satyamurthy Pullela
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
4
Active years
1993–1998
Best venue rank
A*
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 1998 | DATE | CMOS Combinational Circuit Sizing by Stage-wise Tapering. | Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija |
| 1997 | ICCAD | Library-less synthesis for static CMOS combinational logic circuits. | Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw |
| 1997 | ICCD | Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. | Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning |
| 1995 | DAC | Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. | Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi |
| 1994 | ICCAD | RC interconnect synthesis-a moment fitting approach. | Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage |
| 1993 | DAC | Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. | Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage |