Sean Safarpour
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
17
Venues
7
Active years
2004–2011
Best venue rank
A*
Where they publish
Papers
17 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | ASPDAC | From RTL to silicon: The case for automated debug. | Andreas G. Veneris, Brian Keng, Sean Safarpour |
| 2011 | DATE | Automated debugging of SystemVerilog assertions. | Brian Keng, Sean Safarpour, Andreas G. Veneris |
| 2011 | ICCAD | Debugging with dominance: On-the-fly RTL debug solution implications. | Hratch Mangassarian, Andreas G. Veneris, Duncan Exon Smith, Sean Safarpour |
| 2010 | ASPDAC | Managing verification error traces with bounded model debugging. | Sean Safarpour, Andreas G. Veneris, Farid N. Najm |
| 2009 | DAC | The day Sherlock Holmes decided to do EDA. | Andreas G. Veneris, Sean Safarpour |
| 2009 | FPGA | Towards automated ECOs in FPGAs. | Andrew C. Ling, Stephen Dean Brown, Jianwen Zhu, Sean Safarpour |
| 2007 | ASPDAC | Trace Compaction using SAT-based Reachability Analysis. | Sean Safarpour, Andreas G. Veneris, Hratch Mangassarian |
| 2007 | DATE | Maximum circuit activity estimation using pseudo-boolean satisfiability. | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir |
| 2007 | DATE | Abstraction and refinement techniques in automated design debugging. | Sean Safarpour, Andreas G. Veneris |
| 2007 | FMCAD | Improved Design Debugging Using Maximum Satisfiability. | Sean Safarpour, Hratch Mangassarian, Andreas G. Veneris, Mark H. Liffiton, Karem A. Sakallah |
| 2007 | ICCAD | A performance-driven QBF-based iterative logic array representation with applications to verification, debug and test. | Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Marco Benedetti, Duncan Exon Smith |
| 2006 | DAC | Efficient SAT-based Boolean matching for FPGA technology mapping. | Sean Safarpour, Andreas G. Veneris, Gregg Baeckler, Richard Yuan |
| 2006 | DATE | On the relation between simulation-based and SAT-based diagnosis. | Grschwin Fey, Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
| 2006 | ISCAS | Integrating observability don't cares in all-solution SAT solvers. | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler |
| 2005 | ICCAD | Post-verification debugging of hierarchical designs. | Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler |
| 2004 | DATE | Managing Don't Cares in Boolean Satisfiability. | Sean Safarpour, Andreas G. Veneris, Rolf Drechsler, Joanne Lee |
| 2004 | ICCAD | Debugging sequential circuits using Boolean satisfiability. | Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir |