Shang-Wei Tu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
2
Active years
2004–2005
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2005 | ISCAS | RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2004 | ASPDAC | Layout techniques for on-chip interconnect inductance reduction. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |
| 2004 | ISCAS | RLC effects on worst-case switching pattern for on-chip buses. | Shang-Wei Tu, Jing-Yang Jou, Yao-Wen Chang |