| 2024 | ISCAS | Hardware Accelerator for MobileViT Vision Transformer with Reconfigurable Computation. | Shen-Fu Hsiao, Tzu-Hsien Chao, Yen-Che Yuan, Kun-Chih Chen |
| 2024 | ISCAS | Neural Network Acceleration Using Digit-Plane Computation with Early Termination. | Shen-Fu Hsiao, Hou-Chun Kuo, Yu Kuo, Kun-Chih Chen |
| 2022 | ISCAS | Dynamically Swappable Digit-Serial Multi-Precision Deep Neural Network Accelerator with Early Termination. | Shen-Fu Hsiao, Hung-Ching Li, Yu-Che Yen, Po-Chang Li |
| 2021 | ISCAS | Comparison of Digit-Serial and Bit-Level Designs for Acceleration of Convolutional Neural Network Computation. | Shen-Fu Hsiao, Jian-Ming Chen, Yu-Hong Chen, Hung-Ching Li, Yi Hsu |
| 2021 | ISCAS | Efficient Quantization and Multi-Precision Design of Arithmetic Components for Deep Learning. | Shen-Fu Hsiao, Yu-Chang Chen, Yu-Che Yen |
| 2020 | ISCAS | Sparsity-Aware Deep Learning Accelerator Design Supporting CNN and LSTM Operations. | Shen-Fu Hsiao, Hsuan-Jui Chang |
| 2020 | ISCAS | Hardware Efficient Function Computation Based on Optimized Piecewise Polynomial Approximation. | Shen-Fu Hsiao, Chia-Yang Wong, Yu-Chang Chen |
| 2019 | ISCAS | Dual-Precision Acceleration of Convolutional Neural Network Computation with Mixed Input and Output Data Reuse. | Shen-Fu Hsiao, Pei-Hsuan Wu, Jien-Min Chen, Kun-Chih Chen |
| 2018 | DSD | Architectural Exploration of Function Computation Based on Cubic Polynomial Interpolation with Application in Deep Neural Networks. | Shen-Fu Hsiao, Yu-Chang Chen, Hsiang-Hao Liang |
| 2018 | DSD | Design and Implementation of Low-Cost LK Optical Flow Computation for Images of Single and Multiple Levels. | Shen-Fu Hsiao, Chen-Yen Tsai |
| 2018 | ISCAS | Optimization of Lookup Table Size in Table-Bound Design of Function Computation. | Shen-Fu Hsiao, Kun-Chih Chen, Yi-Hau Chen |
| 2014 | DSD | Compression of Lookup Table for Piecewise Polynomial Function Evaluation. | Shen-Fu Hsiao, Chia-Sheng Wen, Po-Han Wu |
| 2014 | DSD | Design and Implementation of Multiple-Vehicle Detection and Tracking Systems with Machine Learning. | Shen-Fu Hsiao, Guan-Fu Yeh, Je-Chi Chen |
| 2014 | ISCAS | Design of low-leakage multi-port SRAM for register file in graphics processing unit. | Shen-Fu Hsiao, Pu-Cheng Wu |
| 2012 | ISCAS | Low latency design of Depth-Image-Based Rendering using hybrid warping and hole-filling. | Shen-Fu Hsiao, Jin-Wen Cheng, Wen-Ling Wang, Guan-Fu Yeh |
| 2011 | ACSSC | Designs of angle-rotation in digital frequency synthesizer/mixer using multi-stage architectures. | Shen-Fu Hsiao, Cheng-Han Lee, Yen-Chun Cheng, Andrew Lee |
| 2010 | ISCAS | A new non-uniform segmentation and addressing remapping strategy for hardware-oriented function evaluators based on polynomial approximation. | Hou-Jen Ko, Shen-Fu Hsiao, Wen-Liang Huang |
| 2009 | ASPDAC | An 8.69 Mvertices/s 278 Mpixels/s tile-based 3D graphics SoC HW/SW development for consumer electronics. | Liang-Bi Chen, Ruei-Ting Gu, Wei-Sheng Huang, Chien-Chou Wang, Wen-Chi Shiue, Tsung-Yu Ho, Yun-Nan Chang, Shen-Fu Hsiao, Chung-Nan Lee, Ing-Jer Huang |
| 2008 | ISCAS | Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. | Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen |
| 2008 | ISCAS | An automatic hardware generator for special arithmetic functions using various ROM-based approximation approaches. | Shen-Fu Hsiao, Ping-Chung Wei, Ching-Pin Lin |
| 2005 | ISCAS | An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. | Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen |
| 2003 | ASPDAC | Design and implementation of a video-oriented network-interface-card system. | Ming-Chih Chen, Shen-Fu Hsiao, Cheng-Hsien Yang |
| 2000 | ICASSP | Low-cost unified architectures for the computation of discrete trigonometric transforms. | Shen-Fu Hsiao, Wei-Ren Shiue |
| 2000 | ISCAS | High-performance multiplexer-based logic synthesis using pass-transistor logic. | Shen-Fu Hsiao, Jia-Siang Yeh, Da-Yen Chen |
| 1999 | ICASSP | A high-throughput, low power architecture and its VLSI implementation for DFT/IDFT computation. | Shen-Fu Hsiao, Wei-Ren Shiue |
| 1999 | ICASSP | New hardware-efficient algorithm and architecture for the computation of 2-D DCT on a linear systolic array. | Shen-Fu Hsiao, Wei-Ren Shiue |
| 1999 | ISCAS | A high-speed constant-factor redundant CORDIC processor without extra correcting or scaling iterations. | Shen-Fu Hsiao |
| 1997 | ICASSP | New unified VLSI architectures for computing DFT and other transforms. | Shen-Fu Hsiao, Chung-Yi Yen |
| 1995 | ICASSP | Adaptive Jacobi method for parallel singular value decompositions. | Shen-Fu Hsiao |
| 1991 | ARITH | The CORDIC Householder algorithm. | Shen-Fu Hsiao, Jean-Marc Delosme |