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Shidhartha Das

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

29

Venues

11

Active years

2003–2021

Best venue rank

A*

Where they publish

Papers

29 indexed papers, newest first.

YearVenueTitleAuthors
2021ISLPEDPower Delivery and Thermal-Aware Arm-Based Multi-Tier 3D Architecture.Lingjun Zhu, Tuan Ta, Rossana Liu, Rahul Mathur, Xiaoqing Xu, Shidhartha Das, Ankit Kaul, Alejandro Rico, Doug Joseph, Brian Cline, Sung Kyu Lim
2021MICROAPOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors.Zhiyao Xie, Xiaoqing Xu, Matt Walker, Joshua Knebel, Kumaraguru Palaniswamy, Nicolas Hebert, Jiang Hu, Huanrui Yang, Yiran Chen, Shidhartha Das
2020IJCNNTraining DNN IoT Applications for Deployment On Analog NVM Crossbars.Fernando Garca-Redondo, Shidhartha Das, Glen Rosendale
2019DATECoDAPT: A Concurrent Data And Power Transceiver for Fully Wireless 3D-ICs.Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019DATEApplications of Computation-In-Memory Architectures based on Memristive Devices.Said Hamdioui, Hoang Anh Du Nguyen, Mottaqiallah Taouil, Abu Sebastian, Manuel Le Gallo, Sandeep Pande, Siebren Schaafsma, Francky Catthoor, Shidhartha Das, Fernando Garca-Redondo, Geethan Karunaratne, Abbas Rahimi, Luca Benini
2019IOLTSRun-time Detection and Mitigation of Power-Noise Viruses.Vasileios Tenentes, Shidhartha Das, Daniele Rossi, Bashir M. Al-Hashimi
2019ISLPEDA Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration.Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2019ISPASSGeST: An Automatic Framework For Generating CPU Stress-Tests.Zacharias Hadjilambrou, Shidhartha Das, Paul N. Whatmough, David M. Bull, Yiannakis Sazeides
2018DATEA high-speed design methodology for inductive coupling links in 3D-ICs.Benjamin J. Fletcher, Shidhartha Das, Terrence S. T. Mak
2018DATELow-power 3D integration using inductive coupling links for neurotechnology applications.Benjamin J. Fletcher, Shidhartha Das, Chi-Sang Poon, Terrence S. T. Mak
2018DATEAn energy-efficient and error-resilient server ecosystem exceeding conservative scaling limits.Georgios Karakonstantis, Konstantinos Tovletoglou, Lev Mukhanov, Hans Vandierendonck, Dimitrios S. Nikolopoulos, Peter Lawthers, Panos K. Koutsovasilis, Manolis Maroudas, Christos D. Antonopoulos, Christos Kalogirou, Nikolaos Bellas, Spyros Lalis, Srikumar Venugopal, Arnau Prat-Prez, Alejandro Lampropulos, Marios Kleanthous, Andreas Diavastos, Zacharias Hadjilambrou, Panagiota Nikolaou, Yiannakis Sazeides, Pedro Trancoso, George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Shidhartha Das
2018DSNMeasuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and DRAMs.Konstantinos Tovletoglou, Lev Mukhanov, Georgios Karakonstantis, Athanasios Chatzidimitriou, George Papadimitriou, Manolis Kaliorakis, Dimitris Gizopoulos, Zacharias Hadjilambrou, Yiannakis Sazeides, Alejandro Lampropulos, Shidhartha Das, Phong Vo
2018MICROLeveraging CPU Electromagnetic Emanations for Voltage Noise Characterization.Zacharias Hadjilambrou, Shidhartha Das, Marco A. Antoniades, Yiannakis Sazeides
2018MICROError Correlation Prediction in Lockstep Processors for Safety-Critical Systems.Emre Ozer, Balaji Venu, Xabier Iturbe, Shidhartha Das, Spyros Lyberis, John Biggs, Peter Harrod, John Penton
2017ISLPEDFrequency and time domain analysis of power delivery network for monolithic 3D ICs.Kyungwook Chang, Shidhartha Das, Saurabh Sinha, Brian Cline, Greg Yeric, Sung Kyu Lim
2017MICROHarnessing voltage margins for energy efficiency in multicore CPUs.George Papadimitriou, Manolis Kaliorakis, Athanasios Chatzidimitriou, Dimitris Gizopoulos, Peter Lawthers, Shidhartha Das
2016DSNA Triple Core Lock-Step (TCLS) ARM Cortex-R5 Processor for Safety-Critical and Ultra-Reliable Applications.Xabier Iturbe, Balaji Venu, Emre Ozer, Shidhartha Das
2015ISLPEDModeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS.Shidhartha Das, Paul N. Whatmough, David M. Bull
2015ISLPEDAnalysis of adaptive clocking technique for resonant supply voltage noise mitigation.Paul N. Whatmough, Shidhartha Das, David M. Bull
2012ASPDACSelective time borrowing for DSP pipelines with hybrid voltage control loop.Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2011DACError-resilient low-power DSP via path-delay shaping.Paul N. Whatmough, Shidhartha Das, David M. Bull, Izzat Darwazeh
2010ISCASA robust FIR filter with in situ error detection.Paul N. Whatmough, Izzat Darwazeh, David M. Bull, Shidhartha Das, Danny Kershaw
2009DACAddressing design margins through error-tolerant circuits.Shidhartha Das, David T. Blaauw, David M. Bull, Krisztin Flautner, Rob Aitken
2009ISCASAdaptive Design for Nanometer Technology.Shidhartha Das, David T. Blaauw
2008DACDVFS in loop accelerators using BLADES.Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David M. Bull
2004DACCircuit-aware architectural simulation.Seokwoo Lee, Shidhartha Das, Valeria Bertacco, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
2004ISLPEDReducing pipeline energy demands with local DVS and dynamic retiming.Seokwoo Lee, Shidhartha Das, Toan Pham, Todd M. Austin, David T. Blaauw, Trevor N. Mudge
2003ICCDOptimal Inductance for On-chip RLC Interconnections.Shidhartha Das, Kanak Agarwal, David T. Blaauw, Dennis Sylvester
2003MICRORazor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation.Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev R. Rao, Toan Pham, Conrad H. Ziesler, David T. Blaauw, Todd M. Austin, Krisztin Flautner, Trevor N. Mudge