Shinya Takamaeda-Yamazaki
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
11
Active years
2014–2026
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ESOP | Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators. | Izumi Tanaka, Ken Sakayori, Shinya Takamaeda-Yamazaki, Naoki Kobayashi |
| 2026 | ISCA | PuDghost: Experimental Analysis of Computation Result Corruption in Processing-Using-Dram Operations on Real Dram Chips and Implications for Future Systems. | Daichi Tokuda, Ismail Emir Yksel, Tatsuya Kubo, Ataberk Olgun, Haocong Luo, Nisa Bostanci, Jikun Wang, A. Giray Yagliki, Shinya Takamaeda-Yamazaki, Onur Mutlu |
| 2026 | ICS | Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding. | Daichi Tokuda, Tatsuya Kubo, Ismail Emir Yuksel, Ataberk Olgun, Haocong Luo, Tomoya Nagatani, Geraldo Francisco Oliveira, Abdullah Giray Yagliki, Mohammad Sadrosadati, Onur Mutlu, Shinya Takamaeda-Yamazaki |
| 2024 | ASPDAC | OSA-HCIM: On-The-Fly Saliency-Aware Hybrid SRAM CIM with Dynamic Precision Configuration. | Yung-Chin Chen, Shimpei Ando, Daichi Fujiki, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka |
| 2024 | ICCAD | PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation. | Wenlun Zhang, Shimpei Ando, Yung-Chin Chen, Satomi Miyagi, Shinya Takamaeda-Yamazaki, Kentaro Yoshioka |
| 2022 | GLOBECOM | Model-based Federated Reinforcement Distillation. | Sefutsu Ryu, Shinya Takamaeda-Yamazaki |
| 2021 | FPL | An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising. | Nobuho Hashimoto, Shinya Takamaeda-Yamazaki |
| 2020 | ISCAS | A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12: 1 SerDes. | Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda |
| 2018 | ICASSP | Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. | Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai |
| 2017 | FCCM | CPRring: A Structure-Aware Ring-Based Checkpointing Architecture for FPGA Computing. | Hoang Gia Vu, Shinya Takamaeda-Yamazaki, Takashi Nakada, Yasuhiko Nakashima |
| 2017 | FPL | FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai |
| 2017 | SGAI | Quantization Error-Based Regularization in Neural Networks. | Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki |
| 2014 | FPL | Ultrasmall: The smallest MIPS soft processor. | Hiroshi Nakatsuka, Yuichiro Tanaka, Thiem Van Chu, Shinya Takamaeda-Yamazaki, Kenji Kise |
| 2014 | FPL | flipSyrup: Cycle-accurate hardware simulation framework on abstract FPGA platforms. | Shinya Takamaeda-Yamazaki, Kenji Kise |