Shoujun Wang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2005–2008
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | ISCAS | A 0.18-m CMOS clock and data recovery circuit with reference-less dual loops. | Miao Li, Tad A. Kwasniewski, Shoujun Wang |
| 2006 | DAC | PELE: pre-emphasis & equalization link estimator to address the effects of signal integrity limitations. | William Bereza, Yuming Tao, Shoujun Wang, Tad A. Kwasniewski, Rakesh H. Patel |
| 2006 | ISCAS | A 0.18m CMOS clock and data recovery circuit with extended operation range. | Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang |
| 2005 | ASPDAC | A 10Gb/s transmitter with multi-tap FIR pre-emphasis in 0.18m CMOS technology. | Miao Li, Tad A. Kwasniewski, Shoujun Wang, Yuming Tao |
| 2005 | ISCAS | A 0.18m CMOS transceiver design for high-speed backplane data communications. | Miao Li, Wenjie Huang, Tad A. Kwasniewski, Shoujun Wang |