Shuichi Sakai
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
54
Venues
24
Active years
1989–2025
Best venue rank
A*
Where they publish
- CICCD8 papers
- CPRDC5 papers
- AICS4 papers
- A*UIST3 papers
- ADATE3 papers
- A*MICRO3 papers
- BASPDAC3 papers
- A*ISCA3 papers
- BCC2 papers
- A*CHI2 papers
- UnrankedSENSYS2 papers
- BEuroPar2 papers
- NationalHiPC2 papers
- ASC2 papers
- CAPSEC1 paper
- CISCAS1 paper
- BFPL1 paper
- CMobiquitous1 paper
- A*IJCAI1 paper
- BSPAA1 paper
- CJSSPP1 paper
- AHPDC1 paper
- ARTSS1 paper
- BICPP1 paper
Papers
54 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | CC | Biotite: A High-Performance Static Binary Translator using Source-Level Information. | Changbin Chen, Shu Sugita, Yotaro Nada, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya |
| 2024 | APSEC | Designing a Reactive Programming Language for Shape-Adaptive Computers. | Yusuke Izawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2024 | CHI | CommuTiles: Shape-Changeable Modular Computer System Using Proximity Wireless Communication. | Masato Goto, Ibuki Sugiyama, Kenta Higuchi, Toshiki Goto, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2024 | UIST | DataPipettor: Touch-Based Information Transfer Interface Using Proximity Wireless Communication. | Shoi To, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2023 | CC | A Sound and Complete Algorithm for Code Generation in Distance-Based ISA. | Shu Sugita, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai |
| 2023 | DATE | TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISA. | Reoma Matsuo, Toru Koizumi, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya |
| 2023 | ISCAS | An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS. | Taichi Amano, Junichiro Kadomoto, Satoshi Mitsuno, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai |
| 2023 | MICRO | Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors. | Toru Koizumi, Ryota Shioya, Shu Sugita, Taichi Amano, Yuya Degawa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2023 | UIST | iKnowde: Interactive Learning Path Generation System Based on Knowledge Dependency Graphs. | Takashi Murayama, Shu Sugita, Hiroyuki Saegusa, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2023 | SENSYS | Poster Abstract: Investigation of Distance Sensing Method Using Magnetic Resonant Coupled Coils for Deformable User Interfaces. | Kenta Higuchi, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2023 | SENSYS | Poster Abstract: Towards a Tiny Digital Displacement Sensor Utilizing Bit-Error Characteristics of Inter-Chip Wireless Bus. | Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2022 | ASPDAC | Deformable Chiplet-Based Computer Using Inductively Coupled Wireless Communication. | Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2022 | DATE | T-SKID: Predicting When to Prefetch Separately from Address Prediction. | Toru Koizumi, Tomoki Nakamura, Yuya Degawa, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya |
| 2021 | ICCD | Compiling and Optimizing Real-world Programs for STRAIGHT ISA. | Toru Koizumi, Shu Sugita, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2021 | ICCD | Accurate and Fast Performance Modeling of Processors with Decoupled Front-end. | Yuya Degawa, Toru Koizumi, Tomoki Nakamura, Ryota Shioya, Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2021 | ICCD | Stochastic Iterative Approximation: Software/hardware techniques for adjusting aggressiveness of approximation. | Tomoki Nakamura, Kazutaka Tomida, Shouta Kouno, Hidetsugu Irie, Shuichi Sakai |
| 2020 | ASPDAC | An Inductively Coupled Wireless Bus for Chiplet-Based Systems. | Junichiro Kadomoto, Satoshi Mitsuno, Hidetsugu Irie, Shuichi Sakai |
| 2020 | CHI | A Self-Sensing Technique Using Inductively-Coupled Coils for Deformable User Interfaces. | Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2020 | FPL | A High-Performance Out-of-Order Soft Processor Without Register Renaming. | Satoshi Mitsuno, Junichiro Kadomoto, Toru Koizumi, Ryota Shioya, Hidetsugu Irie, Shuichi Sakai |
| 2020 | ICCD | Design of Shape-Changeable Chiplet-Based Computers Using an Inductively Coupled Wireless Bus Interface. | Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2019 | ICCD | WiXI: An Inter-Chip Wireless Bus Interface for Shape-Changeable Chiplet-Based Computers. | Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai |
| 2018 | MICRO | STRAIGHT: Hazardless Processor Architecture Without Register Renaming. | Hidetsugu Irie, Toru Koizumi, Akifumi Fukuda, Seiya Akaki, Satoshi Nakae, Yutaro Bessho, Ryota Shioya, Takahiro Notsu, Katsuhiro Yoda, Teruo Ishihara, Shuichi Sakai |
| 2017 | PRDC | Accelerating Integrity Verification on Secure Processors by Promissory Hash. | Mizuki Miyanaga, Hidetsugu Irie, Shuichi Sakai |
| 2016 | ICCD | "Stubborn" strategy to mitigate remaining cache misses. | Hayato Nomura, Hiroyuki Katchi, Hidetsugu Irie, Shuichi Sakai |
| 2016 | Mobiquitous | High-Accuracy Joint Position Estimation and Posture Detection System for Driving. | Takahiro Yamada, Hidetsugu Irie, Shuichi Sakai |
| 2010 | MICRO | Register Cache System Not for Latency Reduction Purpose. | Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai |
| 2009 | ASPDAC | Dependable VLSI: device, design and architecture: how should they cooperate? | Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe |
| 2009 | PRDC | String-Wise Information Flow Tracking against Script Injection Attacks. | Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai |
| 2009 | PRDC | Low-Overhead Architecture for Security Tag. | Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai |
| 2007 | DATE | Utilization of SECDED for soft error and variation-induced defect tolerance in caches. | Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai |
| 2006 | PRDC | SEVA: A Soft-Error- and Variation-Aware Cache Architecture. | Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai |
| 2006 | PRDC | Base Address Recognition with Data Flow Tracking for Injection Attack Detection. | Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai |
| 2005 | ICCD | Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. | Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai |
| 2003 | EuroPar | Compiler-Assisted Thread Level Control Speculation. | Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka |
| 2003 | HiPC | Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. | Yoshimitsu Yanagawa, Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka |
| 2001 | EuroPar | Improving Conditional Branch Prediction on Speculative Multithreading Architectures. | Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka |
| 1999 | IJCAI | Relating Graphical Features with Concept Classes for Automatic News Video Indexing. | Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka |
| 1999 | UIST | Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams. | Masaaki Honda, Takeo Igarashi, Hidehiko Tanaka, Shuichi Sakai |
| 1997 | HiPC | Virtual control channel and its application to the massively parallel computer RWC-1. | Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Shuichi Sakai |
| 1997 | SPAA | Fine-Grain Multithreading with the EM-X Multiprocessor. | Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi |
| 1995 | ICCD | A prototype router for the massively parallel computer RWC-1. | Takashi Yokota, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono, Atsushi Hori, Shuichi Sakai |
| 1995 | ISCA | The EM-X Parallel Computer: Architecture and Basic Performance. | Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi |
| 1995 | ICS | A Macrotask-level Unlimited Speculative Execution on Multiprocessors. | Hayato Yamana, Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi |
| 1995 | JSSPP | Time Space Sharing Scheduling and Architectural Support. | Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jrg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono |
| 1994 | HPDC | Overview of RWC Massively Parallel Computer Project. | Shuichi Sakai |
| 1994 | SC | Nonnumeric search results on the EM-4 distributed-memory multiprocessor. | Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi |
| 1993 | ICS | EMC-Y: Parallel Processing Element Optimizing Communication and Computation. | Yuetsu Kodama, Yasuhito Koumura, Mitsuhisa Sato, Hirohumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi |
| 1993 | ICS | Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation. | Shuichi Sakai, Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Yuetsu Kodama, Mitsuhisa Sato |
| 1992 | ISCA | Thread-based Programming for the EM-4 Hybrid Dataflow Machine. | Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi, Yasuhito Koumura |
| 1992 | RTSS | A priority forwarding scheme for real-time multistage interconnection networks. | Kenji Toda, Kenji Nishida, Shuichi Sakai, Toshio Shimada |
| 1991 | ICPP | Design and Implementation of a Versatile Interconnection Network in the EM-4. | Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi |
| 1991 | SC | Load balancing by function distribution on the EM-4 prototype. | Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi |
| 1990 | ICS | Dataflow computer development in Japan. | Toshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai |
| 1989 | ISCA | An Architecture of a Dataflow Single Chip Processor. | Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba |