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Siva G. Narendra

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

18

Venues

6

Active years

1998–2012

Best venue rank

A*

Where they publish

Papers

18 indexed papers, newest first.

Year	Venue	Title	Authors
2012	ISCAS	Performance analysis of CNFET based circuits in the presence of fabrication imperfections.	Malgorzata Chrzanowska-Jeske, Rehman Ashraf, Rajeev K. Nain, Siva G. Narendra
2010	ASPDAC	Benefits and barriers for probabilistic design.	Siva G. Narendra
2008	ISCAS	Carbon nanotube circuit design choices in the presence of metallic tubes.	Rehman Ashraf, Malgorzata Chrzanowska-Jeske, Siva G. Narendra
2005	ISCAS	Cascode buffer for monolithic voltage conversion operating at high input supply voltages.	Volkan Kursun, Gerhard Schrom, Vivek De, Eby G. Friedman, Siva G. Narendra
2005	ISCAS	Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.	James W. Tschanz, Siva G. Narendra, Ali Keshavarzi, Vivek De
2004	DAC	Design optimizations for microprocessors at low temperature.	Arman Vassighi, Ali Keshavarzi, Siva G. Narendra, Gerhard Schrom, Yibin Ye, Seri Lee, Greg Chrysler, Manoj Sachdev, Vivek De
2004	ISLPED	Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.	Gerhard Schrom, Peter Hazucha, Jae-Hong Hahn, Volkan Kursun, Donald S. Gardner, Siva G. Narendra, Tanay Karnik, Vivek De
2004	VLSID	The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance.	K. Narasimhulu, Siva G. Narendra, V. Ramgopal Rao
2004	VLSID	Design Challenges in Sub-100nm High Performance Microprocessors.	Siva G. Narendra, Vasantha Erraguntla, James W. Tschanz, Nitin Borkar
2003	DAC	Parameter variations and impact on circuits and microarchitecture.	Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De
2003	ISLPED	Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation.	Stephen Tang, Siva G. Narendra, Vivek De
2002	ICCAD	Subthreshold leakage modeling and reduction techniques.	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan
2002	ISLPED	Full-chip sub-threshold leakage power prediction model for sub-0.18 m CMOS.	Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan
2001	ISLPED	Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs.	Ali Keshavarzi, Sean Ma, Siva G. Narendra, Brad Bloechel, K. Mistry, Tahir Ghani, Shekhar Borkar, Vivek De
2001	ISLPED	Scaling of stack effect and its application for leakage reduction.	Siva G. Narendra, Vivek De, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Shekhar Borkar
2001	ISLPED	Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.	James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De
1999	ISLPED	Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.	Ali Keshavarzi, Siva G. Narendra, Shekhar Borkar, Charles F. Hawkins, Kaushik Roy, Vivek De
1998	DAC	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan