| 2015 | ICMV | Coding efficiency of AVS 2.0 for CBAC and CABAC engines. | Jing Cui, Youngkyu Choi, Soo-Ik Chae |
| 2008 | FDL | RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow. | Jinhyun Cho, Soonwoo Choi, Soo-Ik Chae |
| 2007 | DAC | Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. | Kai Huang, Sang-Il Han, Katalin Popovici, Lisane B. de Brisolara, Xavier Guerin, Lei Li, Xiaolang Yan, Soo-Ik Chae, Luigi Carro, Ahmed Amine Jerraya |
| 2007 | SCOPES | Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. | Lisane B. de Brisolara, Sang-Il Han, Xavier Guerin, Luigi Carro, Ricardo Reis, Soo-Ik Chae, Ahmed Amine Jerraya |
| 2006 | ASPDAC | Functional modeling techniques for efficient SW code generation of video codec applications. | Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya |
| 2006 | ASPDAC | Reusable component IP design using refinement-based design environment. | Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae |
| 2006 | DAC | Buffer memory optimization for video codec application modeled in Simulink. | Sang-Il Han, Xavier Guerin, Soo-Ik Chae, Ahmed Amine Jerraya |
| 2006 | RSP | A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment. | Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae |
| 2005 | ASPDAC | A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. | Minho Kim, Ingu Hwang, Soo-Ik Chae |
| 2005 | ISLPED | Complexity reduction in an nRERL microprocessor. | Seokkee Kim, Soo-Ik Chae |
| 2005 | RSP | A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. | Sanggyu Park, Soo-Ik Chae |
| 2004 | DAC | An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. | Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik Chae, Ahmed Amine Jerraya |
| 2001 | ASPDAC | An 8-b nRERL microprocessor for ultra-low-energy applications. | Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae |
| 2000 | ASPDAC | An 88 nRERL serial multiplier for ultra-low-power aplications. | Joonho Lim, Dong-Gyu Kim, Sang-Chul Kang, Soo-Ik Chae |
| 2000 | ISLPED | A three-port nRERL register file for ultra-low-energy applications. | Jun-Ho Kwon, Joonho Lim, Soo-Ik Chae |
| 2000 | ISLPED | Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). | Koichi Nose, Soo-Ik Chae, Takayasu Sakurai |
| 2000 | RSP | Emulator Environment Based on an FPGA Prototyping Board. | Kyung-soo Oh, Sang-yong Yoon, Soo-Ik Chae |
| 1998 | ISLPED | Partial bus-invert coding for power optimization of system level bus. | Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi |
| 1996 | ICASSP | GPD training of the state weighting functions in hidden control neural network. | Kyungmin Na, Soo-Ik Chae |
| 1996 | ICIP | Fast vector quantizer using multiple sorted index tables. | Sun-Young Choi, Soo-Ik Chae |
| 1996 | ICIP | Two-step motion estimation algorithm using low-resolution quantization. | Seongsoo Lee, Soo-Ik Chae |
| 1995 | Interspeech | Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method. | Kyungmin Na, Bumki Jeon, Dong-Il Chang, Soo-Ik Chae, Souguil Ann |
| 1995 | Interspeech | Recurrent neural prediction models for speech recognition. | Kyungmin Na, Jekwan Ryu, Dong-Il Chang, Soo-Ik Chae, Souguil Ann |
| 1994 | ISCAS | Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism. | Joonho Lim, Eel-Wan Lee, Soo-Ik Chae |
| 1994 | ISCAS | A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses. | Seung-Jai Min, Eel-Wan Lee, Soo-Ik Chae |
| 1994 | ISCAS | Stereo Correspondence with Discrete-Time Cellular Neural Networks. | Sungjun Park, Seung-Jai Min, Soo-Ik Chae |
| 1993 | ISCAS | Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm. | Eel-Wan Lee, Jae-Hee Won, Soo-Ik Chae |