| 2025 | ASPDAC | Response Range Optimization for Run-Time Requirement Enforcement on MPSoCs. | Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2025 | BTW | ReProVide: Query Optimisation and Near-Data Processing on Reconfigurable SoCs for Big Data Analysis. | Tobias Hahn, Maximilian S. Langohr, Stefan Meiner, Benedikt Dring, Stefan Wildermann, Klaus Meyer-Wegener, Jrgen Teich |
| 2025 | EWSN | WiP Paper: Utility-Aware Transmission of Sensor Data on Energy-Harvesting IoT Gateways. | Pierre-Louis Sixdenier, Jebacyril Arockiaraj, Stefan Wildermann, Jrgen Teich |
| 2024 | DATE | Range-Based Run-time Requirement Enforcement of Non-Functional Properties on MPSoCs. | Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2024 | DDECS | ABACUS: ASIP-Based Avro Schema-Customizable Parser Acceleration on FPGAs. | Tobias Hahn, Daniel Schll, Stefan Wildermann, Jrgen Teich |
| 2024 | FPL | JSON-CooP: A JSON Decompression/Parsing Co-Design for FPGAs. | Tobias Hahn, Stefan Wildermann, Jrgen Teich |
| 2023 | BTW | An FPGA Avro Parser Generator for Accelerated Data Stream Processing. | Tobias Hahn, Daniel Schll, Stefan Wildermann, Jrgen Teich |
| 2023 | CASES | Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. | Jrg Henkel, Lokesh Siddhu, Lars Bauer, Jrgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jernimo Castrilln, Asif Ali Khan, Hamid Farzaneh, Joo Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng |
| 2023 | FPL | SPEAR-JSON: Selective Parsing of JSON to Enable Accelerated Stream Processing on FPGAs. | Tobias Hahn, Stefan Wildermann, Jrgen Teich |
| 2023 | MEMOCODE | Hybrid Genetic Reinforcement Learning for Generating Run-Time Requirement Enforcers. | Jan Spieck, Pierre-Louis Sixdenier, Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2022 | CCS | Putting IMT to the Test: Revisiting and Expanding Interval Matching Techniques and their Calibration for SCA. | Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Stefan Wildermann, Jrgen Teich |
| 2022 | DATE | Raw Filtering of JSON Data on FPGAs. | Tobias Hahn, Andreas Becher, Stefan Wildermann, Jrgen Teich |
| 2022 | FCCM | Characterization of Side Channels on FPGA-based Off-The-Shelf Boards against Automated Attacks. | Jens Trautmann, Jrgen Teich, Stefan Wildermann |
| 2022 | FPL | Real-Time Waveform Matching with a Digitizer at 10 GS/s. | Jens Trautmann, Nikolaos Patsiatzis, Andreas Becher, Jrgen Teich, Stefan Wildermann |
| 2022 | FPL | Auto-Tuning of Raw Filters for FPGAs. | Tobias Hahn, Stefan Wildermann, Jrgen Teich |
| 2021 | DATE | Approximate Logic Synthesis of Very Large Boolean Networks. | Jorge Echavarria, Stefan Wildermann, Jrgen Teich |
| 2021 | FPL | Choice - A Tunable PUF-Design for FPGAs. | Franz-Josef Streit, Paul Krger, Andreas Becher, Jens Schlumberger, Stefan Wildermann, Jrgen Teich |
| 2021 | MEMOCODE | Enforcement FSMs: specification and verification of non-functional properties of program executions on MPSoCs. | Khalil Esper, Stefan Wildermann, Jrgen Teich |
| 2020 | ASPDAC | Run-Time Enforcement of Non-Functional Application Requirements in Heterogeneous Many-Core Systems. | Jrgen Teich, Behnaz Pourmohseni, Oliver Keszcze, Jan Spieck, Stefan Wildermann |
| 2020 | DAC | Probabilistic Error Propagation through Approximated Boolean Networks. | Jorge Echavarria, Stefan Wildermann, Oliver Keszcze, Jrgen Teich |
| 2020 | DAC | Scenario-Based Soft Real-Time Hybrid Application Mapping for MPSoCs. | Jan Spieck, Stefan Wildermann, Jrgen Teich |
| 2020 | EDBT | SQL Query Processing Using an Integrated FPGA-based Near-Data Accelerator in ReProVide. | Lekshmi B. G., Andreas Becher, Klaus Meyer-Wegener, Stefan Wildermann, Jrgen Teich |
| 2019 | BTW | ReProVide: Towards Utilizing Heterogeneous Partially Reconfigurable Architectures for Near-Memory Data Processing. | Andreas Becher, Achim Herrmann, Stefan Wildermann, Jrgen Teich |
| 2019 | ECRTS | Isolation-Aware Timing Analysis and Design Space Exploration for Predictable and Composable Many-Core Systems. | Behnaz Pourmohseni, Fedor Smirnov, Stefan Wildermann, Jrgen Teich |
| 2019 | RTSS | Thermally Composable Hybrid Application Mapping for Real-Time Applications in Heterogeneous Many-Core Systems. | Behnaz Pourmohseni, Fedor Smirnov, Heba Khdr, Stefan Wildermann, Jrgen Teich, Jrg Henkel |
| 2018 | DAC | Architecture decomposition in system synthesis of heterogeneous many-core systems. | Valentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jrgen Teich, Michael Gla |
| 2018 | DaMoN | Optimistic regular expression matching on FPGAs for near-data processing. | Andreas Becher, Stefan Wildermann, Jrgen Teich |
| 2018 | ICCAD | Design space exploration of multi-output logic function approximations. | Jorge Echavarria, Stefan Wildermann, Jrgen Teich |
| 2018 | ICCAD | Dynamic resource management for heterogeneous many-cores. | Jrg Henkel, Jrgen Teich, Stefan Wildermann, Hussam Amrouch |
| 2017 | RTNS | Predictable run-time mapping reconfiguration for real-time applications on many-core systems. | Behnaz Pourmohseni, Stefan Wildermann, Michael Gla, Jrgen Teich |
| 2017 | SCOPES | Exploiting Predictability in Dynamic Network Communication for Power-Efficient Data Transmission in LTE Radio Systems. | Peter Brand, Jonathan Ah Sue, Johannes Brendel, Joachim Falk, Ralph Hasholzner, Jrgen Teich, Stefan Wildermann |
| 2017 | SCOPES | Automatic Conversion of Simulink Models to SysteMoC Actor Networks. | Martn Letras, Joachim Falk, Stefan Wildermann, Jrgen Teich |
| 2017 | SCOPES | Self-Adaptive FPGA-Based Image Processing Filters Using Approximate Arithmetics. | Jutta Pirkl, Andreas Becher, Jorge Echavarria, Jrgen Teich, Stefan Wildermann |
| 2016 | FCCM | A LUT-Based Approximate Adder. | Andreas Becher, Jorge Echavarria, Daniel Ziener, Stefan Wildermann, Jrgen Teich |
| 2016 | PLDI | ActorX10: an actor library for X10. | Sascha Roloff, Alexander Pppl, Tobias Schwarzer, Stefan Wildermann, Michael Bader, Michael Gla, Frank Hannig, Jrgen Teich |
| 2016 | SCOPES | Design-Time/Run-Time Mapping of Security-Critical Applications in Heterogeneous MPSoCs. | Andreas Weichslgartner, Stefan Wildermann, Johannes Gtzfried, Felix C. Freiling, Michael Gla, Jrgen Teich |
| 2015 | ISORC | Design Methodology and Run-Time Management for Predictable Many-Core Systems. | Stefan Wildermann, Andreas Weichslgartner, Jrgen Teich |
| 2014 | DATE | Multi-objective distributed run-time resource management for many-cores. | Stefan Wildermann, Michael Gla, Jrgen Teich |
| 2013 | DATE | Game-theoretic analysis of decentralized core allocation schemes on many-core systems. | Stefan Wildermann, Tobias Ziermann, Jrgen Teich |
| 2011 | FPL | Unifying Partitioning and Placement for SAT-Based Exploration of Heterogeneous Reconfigurable SoCs. | Stefan Wildermann, Jrgen Teich, Daniel Ziener |
| 2010 | ATC | Self-organizing Computer Vision for Robust Object Tracking in Smart Cameras. | Stefan Wildermann, Andreas Oetken, Jrgen Teich, Zoran A. Salcic |
| 2010 | FPL | A Bus-Based SoC Architecture for Flexible Module Placement on Reconfigurable FPGAs. | Andreas Oetken, Stefan Wildermann, Jrgen Teich, Dirk Koch |
| 2010 | ISORC | A Self-Organizing Distributed Reinforcement Learning Algorithm to Achieve Fair Bandwidth Allocation for Priority-Based Bus Communication. | Tobias Ziermann, Nina Mhleis, Stefan Wildermann, Jrgen Teich |
| 2009 | DATE | CAN+: A new backward-compatible Controller Area Network (CAN) protocol with up to 16 higher data rates. | Tobias Ziermann, Stefan Wildermann, Jrgen Teich |
| 2009 | FPL | Self-organizing multi-cue fusion for FPGA-based embedded imaging. | Stefan Wildermann, Gregor Walla, Tobias Ziermann, Jrgen Teich |
| 2008 | HIS | A Sequential Learning Resource Allocation Network for Image Processing Applications. | Stefan Wildermann, Jrgen Teich |
| 2008 | RSP | Co-design Architecture and Implementation for Point-Based Rendering on FPGAs. | Mateusz Majer, Stefan Wildermann, Josef Angermeier, Stefan Hanke, Jrgen Teich |