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Stephen Brown

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

27

Venues

18

Active years

1990–2021

Best venue rank

A*

Where they publish

Papers

27 indexed papers, newest first.

YearVenueTitleAuthors
2021FPLLeveraging Fine-grained Structured Sparsity for CNN Inference on Systolic Array Architectures.Linqiao Liu, Stephen Brown
2020AMIADevelopment and Implementation of a Patient-Facing, FHIR-based Clinical Decision Support Tool to Support Shared Decision Making for Chronic Pain.Laura H. Marcial, Joshua E. Richardson, Stephanie Rizk, Stephen Brown, Jessica DeFrank, Danny van Leeuwen, Asli Weitkamp, Cheng-Kai Kao, Barry H. Blumenfeld
2020FPGAUsing OpenCL to Enable Software-like Development of an FPGA-Accelerated Biophotonic Cancer Treatment Simulator.Tanner Young-Schultz, Lothar Lilge, Stephen Brown, Vaughn Betz
2020WoWMoMLightweight Timeslot Scheduling Through Periodicity Detection for Increased Scalability of LoRaWAN.Joseph Finnegan, Ronan Farrell, Stephen Brown
2018ISNCCAn Analysis of the Energy Consumption of LPWA-based IoT Devices.Joseph Finnegan, Stephen Brown
2017FPLFISH: Linux system calls for FPGA accelerators.Kevin Nam, Blair Fort, Stephen Brown
2014EUCAutomating the Design of Processor/Accelerator Embedded Systems with LegUp High-Level Synthesis.Blair Fort, Andrew Canis, Jongsok Choi, Nazanin Calagar, Ruolong Lian, Stefan Hadjis, Yu Ting Chen, Mathew Hall, Bain Syrowik, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2014ISCASThe design of low complexity low power pipelined short length Winograd Fourier transforms.Adem Coskun, Izzet Kale, Richard C. S. Morling, Robert Hughes, Stephen Brown, Piero Angeletti
2013CASESFrom software to accelerators with LegUp high-level synthesis.Andrew Canis, Jongsok Choi, Blair Fort, Ruolong Lian, Qijing Huang, Nazanin Calagar, Marcel Gort, Jia Jun Qin, Mark Aldham, Tomasz S. Czajkowski, Stephen Brown, Jason Helge Anderson
2013FCCMThe Effect of Compiler Optimizations on High-Level Synthesis for FPGAs.Qijing Huang, Ruolong Lian, Andrew Canis, Jongsok Choi, Ryan Xi, Stephen Brown, Jason Helge Anderson
2012FCCMImpact of Cache Architecture and Interface on Performance and Area of FPGA-Based Processor/Parallel-Accelerator Systems.Jongsok Choi, Kevin Nam, Andrew Canis, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2012FPGAImpact of FPGA architecture on resource sharing in high-level synthesis.Stefan Hadjis, Andrew Canis, Jason Helge Anderson, Jongsok Choi, Kevin Nam, Stephen Brown, Tomasz S. Czajkowski
2011FPGALegUp: high-level synthesis for FPGA-based processor/accelerator systems.Andrew Canis, Jongsok Choi, Mark Aldham, Victor Zhang, Ahmed Kammoona, Jason Helge Anderson, Stephen Brown, Tomasz S. Czajkowski
2011IJCNNMagnetic resonance imaging estimation of longitudinal relaxation rate change (ΔR1) in dual gradient echo sequences using an adaptive model.Hassan Bagher-Ebadian, Siamak P. Nejad-Davarani, Meser M. Ali, Stephen Brown, Malek Makki, Quan Jiang, Douglas C. Noll, James R. Ewing
2009FPLEnhancements to FPGA design methodology using streaming.Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2008FDLTowards Compilation of Streaming Programs into FPGA Hardware.Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2008FDLStream Programming for FPGAs.Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2007ICSoftOn Digital Search Trees - A Simple Method for Constructing Balanced Binary Trees.Franjo Plavec, Zvonko G. Vranesic, Stephen Brown
2007MASSA Study on Data Aggregation and Reliability in Managing Wireless Sensor Networks.Stephen Brown, Cormac J. Sreenan
2003WCAEUse of HDLs in teaching of computer hardware courses.Zvonko G. Vranesic, Stephen Brown
2000FPGATechnology mapping issues for an FPGA with lookup tables and PLA-like blocks.Alireza Kaviani, Stephen Brown
2000ICPPThe NUMAchine Multiprocessor.R. Grindley, Tarek S. Abdelrahman, Stephen Brown, S. Caranci, D. DeVries, Benjamin Gamsa, A. Grbic, M. Gusat, R. Ho, Orran Krieger, Guy G. Lemieux, K. Loveless, Naraig Manjikian, P. McHardy, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1998DACDesign and Implementation of the NUMAchine Multiprocessor.A. Grbic, Stephen Brown, S. Caranci, R. Grindley, M. Gusat, Guy G. Lemieux, K. Loveless, Naraig Manjikian, Sinisa Srbljic, Michael Stumm, Zvonko G. Vranesic, Zeljko Zilic
1996DACExperience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.Stephen Brown, Naraig Manjikian, Zvonko G. Vranesic, S. Caranci, A. Grbic, R. Grindley, M. Gusat, K. Loveless, Zeljko Zilic, Sinisa Srbljic
1996FPGAHybrid FPGA Architecture.Alireza Kaviani, Stephen Brown
1992ICCDImproving FPGA Routing Architectures Using Architecture and CAD Interactions.Benjamin Tseng, Jonathan Rose, Stephen Brown
1990ICCADA Detailed Router for Field-Programmable Gate Arrays.Stephen Brown, Jonathan Rose, Zvonko G. Vranesic