Subhrashankha Ghosh
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2010–2011
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | FPL | XDL-Based Module Generators for Rapid FPGA Design Implementation. | Subhrashankha Ghosh, Brent E. Nelson |
| 2010 | FPL | Using Hard Macros to Reduce FPGA Compilation Time. | Christopher Lavin, Marc Padilla, Subhrashankha Ghosh, Brent E. Nelson, Brad L. Hutchings, Michael J. Wirthlin |