Sudeep Puligundla
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2010–2015
Best venue rank
A
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | ITC | Platform IO and system memory test using L3 cache based test (CBT) and parallel execution of CPGC Intel BIST engine. | Bruce Querbach, Tan Peter Yanyang, Lovelace Van, David Blankenbeckler, Rahul Khanna, Sudeep Puligundla, Patrick Chiang |
| 2010 | ITC | Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery. | Sudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran |