Sumanta Chaudhuri
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
12
Venues
6
Active years
2007–2024
Best venue rank
A*
Where they publish
Papers
12 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | AAAI | Find the Lady: Permutation and Re-synchronization of Deep Neural Networks. | Carl De Sousa Trias, Mihai Petru Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione |
| 2024 | ICPR | WaterMAS: Sharpness-Aware Maximization for Neural Network Watermarking. | Carl De Sousa Trias, Mihai Mitrea, Attilio Fiandrotti, Marco Cagnazzo, Sumanta Chaudhuri, Enzo Tartaglione |
| 2022 | ICIP | Minconvnets: a New Class of Multiplication-Less Neural Networks. | Xuecan Yang, Sumanta Chaudhuri, Laurence Likforman, Lirida A. B. Naviner |
| 2018 | DAC | A security vulnerability analysis of SoCFPGA architectures. | Sumanta Chaudhuri |
| 2017 | FPGA | Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only). | Sumanta Chaudhuri |
| 2013 | FPL | A variation-adaptive retiming method exploiting reconfigurability. | Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
| 2012 | FPL | A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. | Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung |
| 2010 | FPL | High Density Asynchronous LUT Based on Non-volatile MRAM Technology. | Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer |
| 2009 | FPGA | Diagonal tracks in FPGAs: a performance evaluation. | Sumanta Chaudhuri |
| 2008 | DAC | An 8x8 run-time reconfigurable FPGA embedded in a SoC. | Sumanta Chaudhuri, Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Jean-Luc Danger |
| 2008 | FPGA | Efficient tiling patterns for reconfigurable gate arrays. | Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley |
| 2007 | FPL | Efficient Modeling and Floorplanning of Embedded-FPGA Fabric. | Sumanta Chaudhuri, Jean-Luc Danger, Sylvain Guilley |