Taeko Matsunaga
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
3
Active years
2008–2011
Best venue rank
A
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2011 | ISLPED | Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs. | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
| 2010 | ASPDAC | Multi-operand adder synthesis on FPGAs using generalized parallel counters. | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |
| 2008 | ICCD | Synthesis of parallel prefix adders considering switching activities. | Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga |