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Taiquan Wei

Publication record assembled from the DBLP archive of ranked conferences.

Papers indexed

5

Venues

3

Active years

2025–2026

Best venue rank

A*

Where they publish

Papers

5 indexed papers, newest first.

YearVenueTitleAuthors
2026HPCAMoEntwine: Unleashing the Potential of Wafer-Scale Chips for Large-Scale Expert Parallel Inference.Xinru Tang, Jingxiang Hou, Dingcheng Jiang, Taiquan Wei, Jiaxin Liu, Jinyi Deng, Huizheng Wang, Qize Yang, Haoran Shang, Chao Li, Yang Hu, Shouyi Yin
2026HPCAWATOS: Efficient LLM Training Strategies and Architecture Co-Exploration for Wafer-Scale Chip.Huizheng Wang, Zichuan Wang, Hongbin Wang, Jingxiang Hou, Taiquan Wei, Chao Li, Yang Hu, Shouyi Yin
2026HPCATEMP: A Memory Efficient Physical-Aware Tensor Partition-Mapping Framework on Wafer-Scale Chips.Huizheng Wang, Taiquan Wei, Zichuan Wang, Dingcheng Jiang, Qize Yang, Jiaxin Liu, Jingxiang Hou, Chao Li, Jinyi Deng, Yang Hu, Shouyi Yin
2025ISCAPD Constraint-aware Physical/Logical Topology Co-Design for Network on Wafer.Qize Yang, Taiquan Wei, Sihan Guan, Chengran Li, Haoran Shang, Jinyi Deng, Huizheng Wang, Chao Li, Lei Wang, Yan Zhang, Shouyi Yin, Yang Hu
2025MICROMCBP: A Memory-Compute Efficient LLM Inference Accelerator Leveraging Bit-Slice-enabled Sparsity and Repetitiveness.Huizheng Wang, Zichuan Wang, Zhiheng Yue, Yousheng Long, Taiquan Wei, Jianxun Yang, Yang Wang, Chao Li, Shaojun Wei, Yang Hu, Shouyi Yin