Tak-Kei Lam
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
4
Active years
2010–2016
Best venue rank
A*
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2016 | ASPDAC | Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). | Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu |
| 2015 | DATE | A coupling area reduction technique applying ODC shifting. | Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu |
| 2015 | DATE | A universal macro block mapping scheme for arithmetic circuits. | Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu |
| 2014 | VLSID | Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. | Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu |
| 2012 | DATE | Almost every wire is removable: A modeling and solution for removing any circuit wire. | Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu |
| 2011 | ASPDAC | On applying erroneous clock gating conditions to further cut down power. | Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu |
| 2010 | DAC | ECR: a low complexity generalized error cancellation rewiring scheme. | Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu |