| 1993 | ICCAD | Tri-state bus conflict checking method for ATPG using BDD. | Yasushi Koseko, Takuji Ogihara, Shinichi Murai |
| 1990 | ICCD | Rule-based testability rule check program. | Yasushi Koseko, C. Hiramine, Takuji Ogihara, Shinichi Murai |
| 1990 | ITC | Testable design and support tool for cell based test. | Takuji Ogihara, Yasushi Koseko, Genichi Yonemori, Hiroyuki Kawai |
| 1989 | DAC | MULTES/IS: An Effective and Reliable Test Generation System for Partial Scan and Non-Scan Synchronous Circuits. | Takuji Ogihara, K. Muroi, Genichi Yonemori, Shinichi Murai |
| 1988 | ICCAD | Test generation for sequential circuits using individual initial value propagation. | Takuji Ogihara, Shuichi Saruyama, Shinichi Murai |
| 1987 | DAC | ASTA: LSI Design Management System. | Takuji Ogihara, Hiromi Toyoshima, Shinichi Murai |
| 1985 | DAC | PATEGE: an automatic DC parametric test generation system for series gated ECL circuits. | Takuji Ogihara, Shuichi Saruyama, Shinichi Murai |
| 1983 | DAC | Test generation for scan design circuits with tri-state modules and bidirectional terminals. | Takuji Ogihara, Shinichi Murai, Yuzo Takamatsu, Kozo Kinoshita, Hideo Fujiwara |
| 1981 | DAC | An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2. | Chiyoji Tanaka, Shinichi Murai, Shunichiro Nakamura, Takuji Ogihara, Masayuki Terai, Kozo Kinoshita |