| 2026 | ISCAS | Live Demonstration: Circular Object Recognition with Binary-weight Spiking Neural Networks. | Ryoichi Yuki, Oliver Velasco-Cardenas, Ayane Matsuzaki, Yoshinari Wada, Seiji Adachi, Kota Ando, Tetsuya Asai, Takao Marukame |
| 2024 | IJCNN | Edge AI Online Training Architecture Using Multi-Phase-Quantization Optimizer. | Itsuki Akeno, Hiiro Yamazaki, Tetsuya Asai, Kota Ando |
| 2024 | IJCNN | Out-of-distribution Data Detection using Bayesian Convolutional Neural Network with Variational Inference. | Koki Minagawa, Taisei Saito, Sena Kojima, Kota Ando, Tetsuya Asai |
| 2019 | DICTA | Radiography Contrast Enhancement: Smoothed LHE Filter a Practical Solution for Digital X-Rays with Mach Band. | Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe |
| 2018 | ICASSP | Sparse Disparity Estimation Using Global Phase Only Correlation for Stereo Matching Acceleration. | Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai |
| 2018 | VCIP | Analysis of Smoothed LHE Methods for Processing Images with Optical Illusions. | Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe |
| 2017 | ASPDAC | An image sensor/processor 3D stacked module featuring ThruChip interfaces. | Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura |
| 2017 | FPL | FPGA implementation of edge-guided pattern generation for motion-vector estimation of textureless objects. | Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai |
| 2017 | IJCNN | Exploring optimized accelerator design for binarized convolutional neural networks. | Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura |
| 2017 | ISCAS | Live demonstration: Feature extraction system using restricted Boltzmann machines on FPGA. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid |
| 2017 | SGAI | Quantization Error-Based Regularization in Neural Networks. | Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki |
| 2016 | ISCAS | Memory-error tolerance of scalable and highly parallel architecture for restricted Boltzmann machines in Deep Belief Network. | Kodai Ueyoshi, Takao Marukame, Tetsuya Asai, Masato Motomura, Alexandre Schmid |
| 2014 | FPL | Caching memcached at reconfigurable network interface. | Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura |
| 2010 | ICONIP | Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. | Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | ASPDAC | A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | ICONIP | Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. | Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | IJCNN | A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. | Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya |
| 2009 | ISCAS | On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. | Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose |
| 2009 | ISCAS | Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. | Ken Ueno, Tetsuya Asai, Yoshihito Amemiya |
| 2008 | ICONIP | Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. | Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya |
| 2007 | ICONIP | Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. | Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2007 | IJCNN | Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. | Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2007 | ISCAS | Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
| 2006 | ISCAS | Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron. | Kazuki Nakada, Jun Igarashi, Tetsuya Asai, Hatsuo Hayashi |
| 2005 | IJCNN | Analog current-mode CMOS implementation of central pattern generator for robot locomotion. | Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2005 | IJCNN | Noise performance of single-electron depressing synapses for neuronal synchrony detection. | Takahide Oya, Tetsuya Asai, Ryo Kagaya, Yoshihito Amemiya |
| 2005 | ISCAS | Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. | Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya |
| 2005 | ISCAS | Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. | Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici |
| 2004 | IJCNN | A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. | Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya |
| 2004 | ISCAS | An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. | Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya |
| 2003 | IJCNN | An analog neural oscillator circuit for locomotion controller in quadruped walking robot. | Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya |
| 2002 | SMC | A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. | Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya |
| 2000 | IJCNN | An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. | Tetsuya Asai, Masato Koutani, Yoshihito Amemiya |
| 1998 | KES | An analog integrated circuit for motion detection. | Hiroo Yonezu, Tetsuya Asai, Masahiro Ohtani, Jang-Kyoo Shin, Naoki Ohshima |