Thomas A. Ziaja
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
6
Venues
3
Active years
1999–2009
Best venue rank
A
Where they publish
Papers
6 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2009 | VTS | Efficient Array Characterization in the UltraSPARC T2. | Thomas A. Ziaja, Poh J. Tan |
| 2008 | ITC | Transition Test on UltraSPARC- T2 Microprocessor. | Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen |
| 2007 | ITC | Design for testability features of the SUN microsystems niagara2 CMP/CMT SPARC chip. | Robert F. Molyneaux, Thomas A. Ziaja, Hong Kim, Shahryar Aryani, Sungbae Hwang, Alex Hsieh |
| 2002 | ITC | A Scalable, Low Cost Design-for-Test Architecture for UltraSPARC | Ishwar Parulkar, Thomas A. Ziaja, Rajesh Pendurkar, Anand D'Souza, Amitava Majumdar |
| 2001 | ICCD | Automatic Generation and Validation of Memory Test Models for High Performance Microprocessors. | Kamran Zarrineh, Thomas A. Ziaja, Amitava Majumdar |
| 1999 | ITC | Using LSSD to test modules at the board level. | Thomas A. Ziaja |